sm4e

SM4 Encrypt (A32)

SM4E.32 <Qd>, <Qm>

SM4 encryption step.

Pseudocode Operation

Qd ← SM4_Encrypt(Qd, Qm)

Example

SM4E.32 q0, q2

Encoding

Binary Layout

11001110110000001000

31:12

11:10

9:5

4:0

Format Crypto 2-Reg

Opcode 0xCEC08400

Extension Crypto (SM4)

Operands

Qd
Destination 128-bit SIMD register
Qm
Key

Reference

View in Arm A64 ISA Reference ↗ Arm A64 ISA

Instruction Forms

Encoding	Instruction		ISA		Bit pattern
0xCEC08400	SM4E <Vd>.4S, <Vn>.4S		A64		11001110110000001000 \| 01 \| Rn \| Rd
0x4523E000	SM4E <Zdn>.S, <Zdn>.S, <Zm>.S		A64		01000101 \| 0 \| 0 \| 10001 \| 1 \| 11100 \| 0 \| Zm \| Zdn

Description

SM4 Encode takes input data as a 128-bit vector from the first source SIMD&FP register, and four iterations of the round key held as the elements of the 128-bit vector in the second source SIMD&FP register. It encrypts the data by four rounds, in accordance with the SM4 standard, returning the 128-bit result to the destination SIMD&FP register. This instruction is implemented only when FEAT_SM4 is implemented.

Operation

AArch64.CheckFPAdvSIMDEnabled();

bits(128) Vn = V[n, 128];
bits(32) intval;
bits(128) roundresult;
bits(32) roundkey;

roundresult = V[d, 128];
for index = 0 to 3
    roundkey = Elem[Vn, index, 32];

    intval = roundresult<127:96> EOR roundresult<95:64> EOR roundresult<63:32> EOR roundkey;

    for i = 0 to 3
        Elem[intval, i, 8] = Sbox(Elem[intval, i, 8]);

    intval = intval EOR ROL(intval, 2) EOR ROL(intval, 10) EOR ROL(intval, 18) EOR ROL(intval, 24);
    intval = intval EOR roundresult<31:0>;

    roundresult<31:0> = roundresult<63:32>;
    roundresult<63:32> = roundresult<95:64>;
    roundresult<95:64> = roundresult<127:96>;
    roundresult<127:96> = intval;

V[d, 128] = roundresult;