sha512h2

SHA512 Hash Part 2 (A32)

SHA512H2.64 <Qd>, <Qn>, <Qm>

SHA512 hash update part 2.

Pseudocode Operation

Qd ← SHA512_H_Part2(Qd, Qn, Qm)

Example

SHA512H2.64 q0, q1, q2

Encoding

Binary Layout

11001110011

31:21

Rm

20:16

1

15

0

14

00

13:12

01

11:10

Rn

9:5

Rd

4:0

 

Format Crypto 3-Reg

Opcode 0xCE608400

Extension Crypto (SHA512)

Operands

• Qd
  State
• Qn
  Hash
• Qm
  Data

Related

More in Crypto (SHA512)

Reference

View in Arm A64 ISA Reference ↗ Arm A64 ISA

Instruction Forms

Encoding	Instruction		ISA		Bit pattern
0xCE608400	SHA512H2 <Qd>, <Qn>, <Vm>.2D		A64		11001110011 | Rm | 1 | 0 | 00 | 01 | Rn | Rd

Description

SHA512 Hash update part 2 takes the values from the three 128-bit source SIMD&FP registers and produces a 128-bit output value that combines the sigma0 and majority functions of two iterations of the SHA512 computation. It returns this value to the destination SIMD&FP register. This instruction is implemented only when FEAT_SHA512 is implemented.

Operation

AArch64.CheckFPAdvSIMDEnabled();

bits(128) Vtmp;
bits(64) NSigma0;
bits(128) x = V[n, 128];
bits(128) y = V[m, 128];
bits(128) w = V[d, 128];

NSigma0 = ROR(y<63:0>, 28) EOR ROR(y<63:0>, 34) EOR ROR(y<63:0>, 39);
Vtmp<127:64> = (x<63:0> AND y<127:64>) EOR (x<63:0> AND y<63:0>) EOR (y<127:64> AND y<63:0>);
Vtmp<127:64> = (Vtmp<127:64> + NSigma0 + w<127:64>);
NSigma0 = ROR(Vtmp<127:64>, 28) EOR ROR(Vtmp<127:64>, 34) EOR ROR(Vtmp<127:64>, 39);
Vtmp<63:0> = ((Vtmp<127:64> AND y<63:0>) EOR (Vtmp<127:64> AND y<127:64>) EOR (y<127:64> AND y<63:0>));
Vtmp<63:0> = (Vtmp<63:0> + NSigma0 + w<63:0>);

V[d, 128] = Vtmp;