orn.w

Bitwise OR NOT (Wide)

ORN.W <Rd>, <Rn>, <Operand2>

Thumb-2 32-bit OR NOT.

Details

Bitwise OR NOT: computes Rd = Rn | ~Operand2, performing a logical OR between Rn and the bitwise NOT of Operand2. The N and Z flags are updated based on the result; C is updated by the shifter; V is unaffected. This is a Thumb-2 (32-bit) instruction available in T32 execution state.

Pseudocode Operation

result ← Rn | (NOT Operand2)
Rd ← result
N ← result[31]
Z ← (result == 0)
C ← CarryOut(NOT Operand2)
V ← unchanged

Example

ORN.W r0, r1, r2

Encoding

Binary Layout
1110101
0011
0
Rn
0
imm3
Rd
imm2
stype
Rm
 
Format Thumb2 Data Proc
Opcode 0xEA600000
Extension T32 (Thumb2)

Operands

  • Rd
    Destination general-purpose register
  • Rn
    First source / base general-purpose register
  • Operand2
    Flexible second operand (register or shifted register)

Reference (Arm AArch32 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0xF0600000 ORN{<c>}{<q>} {<Rd>,} <Rn>, #<const> T32 11110 | i | 0 | 0011 | 0 | Rn | 0 | imm3 | Rd | imm8
0xEA600030 ORN{<c>}{<q>} {<Rd>,} <Rn>, <Rm>, RRX T32 1110101 | 0011 | 0 | Rn | 0 | 000 | Rd | 00 | 11 | Rm
0xEA600000 ORN{<c>}{<q>} {<Rd>,} <Rn>, <Rm> {, <shift> #<amount>} T32 1110101 | 0011 | 0 | Rn | 0 | imm3 | Rd | imm2 | stype | Rm

Description

Bitwise OR NOT (register) performs a bitwise (inclusive) OR of a register value and the complement of an optionally-shifted register value, and writes the result to the destination register. It can optionally update the condition flags based on the result.

Operation

if ConditionPassed() then
    EncodingSpecificOperations();
    (shifted, carry) = Shift_C(R[m], shift_t, shift_n, PSTATE.C);
    result = R[n] OR NOT(shifted);
    R[d] = result;
    if setflags then
        PSTATE.N = result<31>;
        PSTATE.Z = IsZeroBit(result);
        PSTATE.C = carry;
        // PSTATE.V unchanged