vrshr

Vector Rounding Shift Right

VRSHR<c>.<dt> <Qd>, <Qm>, #<imm>

Shifts right with rounding based on immediate.

Details

Shifts each element in the source register right by the immediate shift amount with rounding (the bit at the shift position and all bits to the right are rounded according to ARM rounding rules). Results are stored in the destination register. No condition flags are modified. This is a NEON instruction available in both A32 and T32 instruction sets.

Pseudocode Operation

for i = 0 to elements_in_Qd - 1
  shift_amount ← imm6
  if shift_amount >= element_size then
    Qd[i] ← 0
  else
    rounding_bit ← (Qm[i] >> (shift_amount - 1)) & 1
    Qd[i] ← (Qm[i] >> shift_amount) + rounding_bit
  endif
endfor

Example

VRSHR.dt q0, q2, #16

Encoding

Binary Layout
1111001
U
1
D
imm6
Vd
0010
L
0
M
1
Vm
 
Format NEON Shift
Opcode 0xF2800210
Extension NEON (SIMD)

Operands

  • Qd
    Destination 128-bit SIMD register
  • Qm
    Second source 128-bit SIMD register
  • imm
    Signed immediate value

Reference (Arm AArch32 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0xF2800210 VRSHR{<c>}{<q>}.<type><size> {<Dd>,} <Dm>, #<imm> A32 1111001 | U | 1 | D | imm6 | Vd | 0010 | L | 0 | M | 1 | Vm
0xF2800250 VRSHR{<c>}{<q>}.<type><size> {<Qd>,} <Qm>, #<imm> A32 1111001 | U | 1 | D | imm6 | Vd | 0010 | L | 1 | M | 1 | Vm
0xEF800210 VRSHR{<c>}{<q>}.<type><size> {<Dd>,} <Dm>, #<imm> T32 111 | U | 11111 | D | imm6 | Vd | 0010 | L | 0 | M | 1 | Vm
0xEF800250 VRSHR{<c>}{<q>}.<type><size> {<Qd>,} <Qm>, #<imm> T32 111 | U | 11111 | D | imm6 | Vd | 0010 | L | 1 | M | 1 | Vm
0xF2200110 VRSHR{<c>}{<q>}.<dt> <Dd>, <Dm>, #0 A32 1111001 | 0 | 0 | D | 10 | Vn | Vd | 0001 | N | 0 | M | 1 | Vm
0xF2200150 VRSHR{<c>}{<q>}.<dt> <Qd>, <Qm>, #0 A32 1111001 | 0 | 0 | D | 10 | Vn | Vd | 0001 | N | 1 | M | 1 | Vm
0xEF200110 VRSHR{<c>}{<q>}.<dt> <Dd>, <Dm>, #0 T32 111 | 0 | 11110 | D | 10 | Vn | Vd | 0001 | N | 0 | M | 1 | Vm
0xEF200150 VRSHR{<c>}{<q>}.<dt> <Qd>, <Qm>, #0 T32 111 | 0 | 11110 | D | 10 | Vn | Vd | 0001 | N | 1 | M | 1 | Vm

Description

Vector Rounding Shift Right takes each element in a vector, right shifts them by an immediate value, and places the rounded results in the destination vector. For truncated results, see VSHR. The operand and result elements must be the same size, and can be any one of: Depending on settings in the CPACR, NSACR, and HCPTR registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be undefined, or trapped to Hyp mode. For more information see Enabling Advanced SIMD and floating-point support.

Operation

if ConditionPassed() then
    EncodingSpecificOperations();  CheckAdvSIMDEnabled();
    round_const = 1 << (shift_amount - 1);
    for r = 0 to regs-1
        for e = 0 to elements-1
            result = (Int(Elem[D[m+r],e,esize], unsigned) + round_const) >> shift_amount;
            Elem[D[d+r],e,esize] = result<esize-1:0>;