vrshr

Vector Rounding Shift Right

VRSHR<c>.<dt> <Qd>, <Qm>, #<imm>

Shifts right with rounding based on immediate.

Pseudocode Operation

for i = 0 to elements_in_Qd - 1
  shift_amount ← imm6
  if shift_amount >= element_size then
    Qd[i] ← 0
  else
    rounding_bit ← (Qm[i] >> (shift_amount - 1)) & 1
    Qd[i] ← (Qm[i] >> shift_amount) + rounding_bit
  endif
endfor

Example

VRSHR.dt q0, q2, #16

Encoding

Binary Layout

1111001

31:25

U

24

1

23

D

22

imm6

21:16

Vd

15:12

0010

11:8

L

7

0

6

M

5

1

4

Vm

3:0

 

Format NEON Shift

Opcode 0xF2800210

Extension NEON (SIMD)

Operands

• Qd
  Destination 128-bit SIMD register
• Qm
  Second source 128-bit SIMD register
• imm
  Signed immediate value

Related

More in NEON (SIMD)

Reference

View in Arm A64 ISA Reference ↗ Arm AArch32 ISA

Instruction Forms

Encoding	Instruction		ISA		Bit pattern
0xF2800210	VRSHR{<c>}{<q>}.<type><size> {<Dd>,} <Dm>, #<imm>		A32		1111001 | U | 1 | D | imm6 | Vd | 0010 | L | 0 | M | 1 | Vm
0xF2800250	VRSHR{<c>}{<q>}.<type><size> {<Qd>,} <Qm>, #<imm>		A32		1111001 | U | 1 | D | imm6 | Vd | 0010 | L | 1 | M | 1 | Vm
0xEF800210	VRSHR{<c>}{<q>}.<type><size> {<Dd>,} <Dm>, #<imm>		T32		111 | U | 11111 | D | imm6 | Vd | 0010 | L | 0 | M | 1 | Vm
0xEF800250	VRSHR{<c>}{<q>}.<type><size> {<Qd>,} <Qm>, #<imm>		T32		111 | U | 11111 | D | imm6 | Vd | 0010 | L | 1 | M | 1 | Vm
0xF2200110	VRSHR{<c>}{<q>}.<dt> <Dd>, <Dm>, #0		A32		1111001 | 0 | 0 | D | 10 | Vn | Vd | 0001 | N | 0 | M | 1 | Vm
0xF2200150	VRSHR{<c>}{<q>}.<dt> <Qd>, <Qm>, #0		A32		1111001 | 0 | 0 | D | 10 | Vn | Vd | 0001 | N | 1 | M | 1 | Vm
0xEF200110	VRSHR{<c>}{<q>}.<dt> <Dd>, <Dm>, #0		T32		111 | 0 | 11110 | D | 10 | Vn | Vd | 0001 | N | 0 | M | 1 | Vm
0xEF200150	VRSHR{<c>}{<q>}.<dt> <Qd>, <Qm>, #0		T32		111 | 0 | 11110 | D | 10 | Vn | Vd | 0001 | N | 1 | M | 1 | Vm

Description

Vector Rounding Shift Right takes each element in a vector, right shifts them by an immediate value, and places the rounded results in the destination vector. For truncated results, see VSHR. The operand and result elements must be the same size, and can be any one of: Depending on settings in the CPACR, NSACR, and HCPTR registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be undefined, or trapped to Hyp mode. For more information see Enabling Advanced SIMD and floating-point support.

Operation

if ConditionPassed() then
    EncodingSpecificOperations();  CheckAdvSIMDEnabled();
    round_const = 1 << (shift_amount - 1);
    for r = 0 to regs-1
        for e = 0 to elements-1
            result = (Int(Elem[D[m+r],e,esize], unsigned) + round_const) >> shift_amount;
            Elem[D[d+r],e,esize] = result<esize-1:0>;