insr

SVE Insert Scalar

INSR <Zdn>.<T>, <R><m>

Inserts scalar into bottom of vector, shifting other elements up.

Pseudocode Operation

elements ← VL / esize
for i = elements - 1 downto 1
  Zdn[i] ← Zdn[i-1]
Zdn[0] ← Rm

Example

INSR z0.s.T, Rm

Encoding

Binary Layout

00000101

31:24

size

23:22

100100001110

21:10

9:5

Zdn

4:0

Format SVE Move

Opcode 0x05243800

Extension SVE

Operands

Zdn
Combined destination/source scalable vector register (SVE)
Rm
Scalar Src

Reference

View in Arm A64 ISA Reference ↗ Arm A64 ISA

Instruction Forms

Encoding	Instruction		ISA		Bit pattern
0x05243800	INSR <Zdn>.<T>, <R><m>		A64		00000101 \| size \| 100100001110 \| Rm \| Zdn
0x05343800	INSR <Zdn>.<T>, <V><m>		A64		00000101 \| size \| 110100001110 \| Vm \| Zdn

Description

Shift the destination vector left by one element, and then place a copy of the least-significant bits of the general-purpose register in element 0 of the destination vector. This instruction is unpredicated.

Operation

CheckSVEEnabled();
constant integer VL = CurrentVL;
constant integer PL = VL DIV 8;
bits(VL) dest = Z[dn, VL];
bits(esize) src = X[m, esize];
Z[dn, VL] = dest<(VL-esize)-1:0> : src;