insr

SVE Insert Scalar

INSR <Zdn>.<T>, <R><m>

Inserts scalar into bottom of vector, shifting other elements up.

Details

Inserts a scalar register value into the bottom element of a SVE vector, shifting all other elements upward (toward higher element indices), with the top element discarded. This instruction operates only in AArch64 state and does not modify the condition flags.

Pseudocode Operation

elements ← VL / esize
for i = elements - 1 downto 1
  Zdn[i] ← Zdn[i-1]
Zdn[0] ← Rm

Example

INSR z0.s.T, Rm

Encoding

Binary Layout

00000101

size

100100001110

Zdn

Format SVE Move

Opcode 0x05243800

Extension SVE

Operands

Zdn
Combined destination/source scalable vector register (SVE)
Rm
Scalar Src

Reference (Arm A64 ISA)

Instruction Forms

Encoding	Instruction		ISA		Bit pattern
0x05243800	INSR <Zdn>.<T>, <R><m>		A64		00000101 \| size \| 100100001110 \| Rm \| Zdn
0x05343800	INSR <Zdn>.<T>, <V><m>		A64		00000101 \| size \| 110100001110 \| Vm \| Zdn

Description

Shift the destination vector left by one element, and then place a copy of the least-significant bits of the general-purpose register in element 0 of the destination vector. This instruction is unpredicated.

Operation

CheckSVEEnabled();
constant integer VL = CurrentVL;
constant integer PL = VL DIV 8;
bits(VL) dest = Z[dn, VL];
bits(esize) src = X[m, esize];
Z[dn, VL] = dest<(VL-esize)-1:0> : src;