smlabt

Signed Multiply Accumulate (Bottom x Top)

SMLABT<c> <Rd>, <Rn>, <Rm>, <Ra>

Accumulates (Rn.B * Rm.T) into Ra.

Pseudocode Operation

temp ← SignExtend(Rn[15:0], 32) * SignExtend(Rm[31:16], 32);
result ← temp + Ra;
if OverflowFrom_Addition(temp, Ra) then Q ← 1; end if;
Rd ← result;

Example

SMLABT r0, r1, r2, r5

Encoding

Binary Layout
cond
31:28
00010
27:23
00
22:21
0
20
Rd
19:16
Ra
15:12
Rm
11:8
1
7
1
6
0
5
0
4
Rn
3:0
 
Format Multiply
Opcode 0x010000C0
Extension A32 (DSP)

Operands

  • Rd
    Destination general-purpose register
  • Rn
    First source / base general-purpose register
  • Rm
    Second source / offset general-purpose register
  • Ra
    Acc

Related

More in A32 (DSP)

Reference

View in Arm A64 ISA Reference ↗ Arm AArch32 ISA

Instruction Forms

Encoding Instruction ISA Bit pattern
0x010000C0 SMLABT{<c>}{<q>} <Rd>, <Rn>, <Rm>, <Ra> A32 cond | 00010 | 00 | 0 | Rd | Ra | Rm | 1 | 1 | 0 | 0 | Rn
0xFB100010 SMLABT{<c>}{<q>} <Rd>, <Rn>, <Rm>, <Ra> T32 111110110 | 001 | Rn | Ra | Rd | 00 | 0 | 1 | Rm

Description

Signed Multiply Accumulate (halfwords) performs a signed multiply accumulate operation. The multiply acts on two signed 16-bit quantities, taken from either the bottom or the top half of their respective source registers. The other halves of these source registers are ignored. The 32-bit product is added to a 32-bit accumulate value and the result is written to the destination register. If overflow occurs during the addition of the accumulate value, the instruction sets PSTATE.Q to 1. It is not possible for overflow to occur during the multiplication.

Operation

if ConditionPassed() then
    EncodingSpecificOperations();
    operand1 = if n_high then R[n]<31:16> else R[n]<15:0>;
    operand2 = if m_high then R[m]<31:16> else R[m]<15:0>;
    result = SInt(operand1) * SInt(operand2) + SInt(R[a]);
    R[d] = result<31:0>;
    if result != SInt(result<31:0>) then  // Signed overflow
        PSTATE.Q = '1';