shadd8

Signed Halving Add 8

SHADD8<c> <Rd>, <Rn>, <Rm>

Signed add and halving (average) of 4 bytes.

Details

Performs parallel addition of four signed 8-bit bytes from Rn and Rm, then arithmetically shifts each result right by 1 bit (halving), storing in Rd. No saturation occurs; results are always in the range [−128, 127]. No condition flags are affected. Execution restricted to A32 with DSP extension; requires ARMv6 or later.

Pseudocode Operation

Rd[31:24] ← (SignExtend(Rn[31:24]) + SignExtend(Rm[31:24])) >> 1
Rd[23:16] ← (SignExtend(Rn[23:16]) + SignExtend(Rm[23:16])) >> 1
Rd[15:8] ← (SignExtend(Rn[15:8]) + SignExtend(Rm[15:8])) >> 1
Rd[7:0] ← (SignExtend(Rn[7:0]) + SignExtend(Rm[7:0])) >> 1

Example

SHADD8 r0, r1, r2

Encoding

Binary Layout
cond
01100
011
Rn
Rd
1
1
1
1
1
00
1
Rm
 
Format SIMD Integer
Opcode 0x06300F90
Extension A32 (DSP)

Operands

  • Rd
    Destination general-purpose register
  • Rn
    First source / base general-purpose register
  • Rm
    Second source / offset general-purpose register

Reference (Arm AArch32 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0x06300F90 SHADD8{<c>}{<q>} {<Rd>,} <Rn>, <Rm> A32 cond | 01100 | 011 | Rn | Rd | 1 | 1 | 1 | 1 | 1 | 00 | 1 | Rm
0xFA80F020 SHADD8{<c>}{<q>} {<Rd>,} <Rn>, <Rm> T32 111110101 | 000 | Rn | 1111 | Rd | 0 | 0 | 1 | 0 | Rm

Description

Signed Halving Add 8 performs four signed 8-bit integer additions, halves the results, and writes the results to the destination register.

Operation

if ConditionPassed() then
    EncodingSpecificOperations();
    sum1 = SInt(R[n]<7:0>) + SInt(R[m]<7:0>);
    sum2 = SInt(R[n]<15:8>) + SInt(R[m]<15:8>);
    sum3 = SInt(R[n]<23:16>) + SInt(R[m]<23:16>);
    sum4 = SInt(R[n]<31:24>) + SInt(R[m]<31:24>);
    R[d]<7:0>   = sum1<8:1>;
    R[d]<15:8>  = sum2<8:1>;
    R[d]<23:16> = sum3<8:1>;
    R[d]<31:24> = sum4<8:1>;