sbc

Subtract with Carry (A32)

SBC{S}<c> <Rd>, <Rn>, <Operand2>

Calculates Rd = Rn - Operand2 - NOT(Carry).

Pseudocode Operation

result ← Rn - Operand2 - NOT(C);
Rd ← result;
if S then
  N ← result[31];
  Z ← (result == 0);
  C ← NOT(BorrowFrom(Rn - Operand2 - NOT(C)));
  V ← OverflowFrom(Rn - Operand2 - NOT(C));
endif;

Example

SBC r0, r1, r2

Encoding

Binary Layout

cond

31:28

0010

27:24

110

23:21

19:16

15:12

imm12

11:0

Format Data Proc

Opcode 0x02C00000

Extension A32 (Base)

Operands

Rd
Destination general-purpose register
Rn
First source / base general-purpose register
Operand2
Flexible second operand (register or shifted register)

Other forms of sbc

sbc Subtract with Carry

Reference

View in Arm A64 ISA Reference ↗ Arm AArch32 ISA

Instruction Forms

Encoding	Instruction	ISA	Bit pattern
0x02C00000	SBC{<c>}{<q>} {<Rd>,} <Rn>, #<const>	A32	cond \| 0010 \| 110 \| 0 \| Rn \| Rd \| imm12
0xF1600000	SBC{<c>}{<q>} {<Rd>,} <Rn>, #<const>	T32	11110 \| i \| 0 \| 1011 \| 0 \| Rn \| 0 \| imm3 \| Rd \| imm8
0x00C00060	SBC{<c>}{<q>} {<Rd>,} <Rn>, <Rm>, RRX	A32	cond \| 0000 \| 110 \| 0 \| Rn \| Rd \| 00000 \| 11 \| 0 \| Rm
0x00C00000	SBC{<c>}{<q>} {<Rd>,} <Rn>, <Rm> {, <shift> #<amount>}	A32	cond \| 0000 \| 110 \| 0 \| Rn \| Rd \| imm5 \| stype \| 0 \| Rm
0x4180	SBC<c>{<q>} {<Rdn>,} <Rdn>, <Rm>	T32	010000 \| 0110 \| Rm \| Rdn
0xEB600030	SBC{<c>}{<q>} {<Rd>,} <Rn>, <Rm>, RRX	T32	1110101 \| 1011 \| 0 \| Rn \| 0 \| 000 \| Rd \| 00 \| 11 \| Rm
0xEB600000	SBC<c>.W {<Rd>,} <Rn>, <Rm>	T32	1110101 \| 1011 \| 0 \| Rn \| 0 \| imm3 \| Rd \| imm2 \| stype \| Rm
0x00C00010	SBC{<c>}{<q>} {<Rd>,} <Rn>, <Rm>, <shift> <Rs>	A32	cond \| 0000 \| 110 \| 0 \| Rn \| Rd \| Rs \| 0 \| stype \| 1 \| Rm

Description

Subtract with Carry (immediate) subtracts an immediate value and the value of NOT (Carry flag) from a register value, and writes the result to the destination register. If the destination register is not the PC, the SBCS variant of the instruction updates the condition flags based on the result. The field descriptions for <Rd> identify the encodings where the PC is permitted as the destination register. ARM deprecates any use of these encodings. However, when the destination register is the PC:

Operation

if ConditionPassed() then
    EncodingSpecificOperations();
    (result, nzcv) = AddWithCarry(R[n], NOT(imm32), PSTATE.C);
    if d == 15 then          // Can only occur for A32 encoding
        if setflags then
            ALUExceptionReturn(result);
        else
            ALUWritePC(result);
    else
        R[d] = result;
        if setflags then
            PSTATE.<N,Z,C,V> = nzcv;

sbc