cmge

Vector Compare Greater Than or Equal

CMGE <Vd>.<T>, <Vn>.<T>, <Vm>.<T>

Compares elements (Vn >= Vm).

Details

Compares each signed element of Vn with the corresponding element of Vm; if Vn[i] >= Vm[i], sets all bits in Vd[i] to 1; otherwise sets them to 0. The comparison is signed. Condition flags are not affected. This is a NEON instruction available in AArch64 execution state.

Pseudocode Operation

for i = 0 to elements_in_vector - 1
  if (Vn[i] >= Vm[i]) then
    Vd[i] ← all_ones
  else
    Vd[i] ← all_zeros

Example

CMGE v0.4s.T, v1.4s.T, v2.4s.T

Encoding

Binary Layout
0
Q
0
01110
size
1
Rm
0011
1
1
Rn
Rd
 
Format SIMD Three Register
Opcode 0x0E203C00
Extension NEON (SIMD)

Operands

  • Vd
    Destination SIMD/FP vector register
  • Vn
    First source SIMD/FP vector register
  • Vm
    Second source SIMD/FP vector register

Reference (Arm A64 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0x5EE03C00 CMGE D<d>, D<n>, D<m> A64 01 | 0 | 11110 | 11 | 1 | Rm | 0011 | 1 | 1 | Rn | Rd
0x0E203C00 CMGE <Vd>.<T>, <Vn>.<T>, <Vm>.<T> A64 0 | Q | 0 | 01110 | size | 1 | Rm | 0011 | 1 | 1 | Rn | Rd
0x7EE08800 CMGE D<d>, D<n>, #0 A64 01 | 1 | 11110 | 11 | 100000100 | 0 | 10 | Rn | Rd
0x2E208800 CMGE <Vd>.<T>, <Vn>.<T>, #0 A64 0 | Q | 1 | 01110 | size | 100000100 | 0 | 10 | Rn | Rd

Description

Compare signed Greater than or Equal (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first signed integer value is greater than or equal to the second signed integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero. Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = V[n, datasize];
bits(datasize) operand2 = V[m, datasize];
bits(datasize) result;
integer element1;
integer element2;
boolean test_passed;

for e = 0 to elements-1
    element1 = Int(Elem[operand1, e, esize], unsigned);
    element2 = Int(Elem[operand2, e, esize], unsigned);
    test_passed = if cmp_eq then element1 >= element2 else element1 > element2;
    Elem[result, e, esize] = if test_passed then Ones(esize) else Zeros(esize);

V[d, datasize] = result;