bic

Bit Clear (A32)

BIC{S}<c> <Rd>, <Rn>, <Rm> {, <shift>}

Performs AND NOT (Rd = Rn & ~Rm).

Details

Performs a bitwise AND with the complement (NOT) of Rm, computing Rd = Rn AND ~Rm (bit clear). If the S suffix is present, condition flags are updated: N and Z set based on the result, C set to shifter carry-out, and V is unaffected. Executes in A32 only.

Pseudocode Operation

result ← Rn AND NOT(Rm shifted by shift_amount)
Rd ← result
if S == 1 then
  N ← result[31]
  Z ← (result == 0)
  C ← shifter_carry_out
else
  condition_flags unchanged

Example

BIC r0, r1, r2

Encoding

Binary Layout
cond
00011
10
0
Rn
Rd
imm5
stype
0
Rm
 
Format Data Proc
Opcode 0x01C00000
Extension A32 (Base)

Operands

  • Rd
    Destination general-purpose register
  • Rn
    First source / base general-purpose register
  • Rm
    Second source / offset general-purpose register

Reference (Arm AArch32 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0x03C00000 BIC{<c>}{<q>} {<Rd>,} <Rn>, #<const> A32 cond | 00111 | 10 | 0 | Rn | Rd | imm12
0xF0200000 BIC{<c>}{<q>} {<Rd>,} <Rn>, #<const> T32 11110 | i | 0 | 0001 | 0 | Rn | 0 | imm3 | Rd | imm8
0x01C00060 BIC{<c>}{<q>} {<Rd>,} <Rn>, <Rm>, RRX A32 cond | 00011 | 10 | 0 | Rn | Rd | 00000 | 11 | 0 | Rm
0x01C00000 BIC{<c>}{<q>} {<Rd>,} <Rn>, <Rm> {, <shift> #<amount>} A32 cond | 00011 | 10 | 0 | Rn | Rd | imm5 | stype | 0 | Rm
0x4380 BIC<c>{<q>} {<Rdn>,} <Rdn>, <Rm> T32 010000 | 1110 | Rm | Rdn
0xEA200030 BIC{<c>}{<q>} {<Rd>,} <Rn>, <Rm>, RRX T32 1110101 | 0001 | 0 | Rn | 0 | 000 | Rd | 00 | 11 | Rm
0xEA200000 BIC<c>.W {<Rd>,} <Rn>, <Rm> T32 1110101 | 0001 | 0 | Rn | 0 | imm3 | Rd | imm2 | stype | Rm
0x01C00010 BIC{<c>}{<q>} {<Rd>,} <Rn>, <Rm>, <shift> <Rs> A32 cond | 00011 | 10 | 0 | Rn | Rd | Rs | 0 | stype | 1 | Rm

Description

Bitwise Bit Clear (register) performs a bitwise AND of a register value and the complement of an optionally-shifted register value, and writes the result to the destination register. If the destination register is not the PC, the BICS variant of the instruction updates the condition flags based on the result. The field descriptions for <Rd> identify the encodings where the PC is permitted as the destination register. Arm deprecates any use of these encodings. However, when the destination register is the PC:

Operation

if ConditionPassed() then
    EncodingSpecificOperations();
    (shifted, carry) = Shift_C(R[m], shift_t, shift_n, PSTATE.C);
    result = R[n] AND NOT(shifted);
    if d == 15 then          // Can only occur for A32 encoding
        if setflags then
            ALUExceptionReturn(result);
        else
            ALUWritePC(result);
    else
        R[d] = result;
        if setflags then
            PSTATE.N = result<31>;
            PSTATE.Z = IsZeroBit(result);
            PSTATE.C = carry;
            // PSTATE.V unchanged