vadd

Vector Add (Integer)

VADD<c>.I<size> <Qd>, <Qn>, <Qm>

Adds integer elements of two vectors.

Pseudocode Operation

for each element i in Qd:
  Qd[i] ← Qn[i] + Qm[i]

Example

VADD.Isize q0, q1, q2

Encoding

Binary Layout

1111001

31:25

size

21:20

19:16

15:12

1000

11:8

3:0

Format NEON 3-Reg

Opcode 0xF2000800

Extension NEON (SIMD)

Operands

Qd
Destination 128-bit SIMD register
Qn
First source 128-bit SIMD register
Qm
Second source 128-bit SIMD register

Other forms of vadd

vadd Vector Add (VFP)
vadd Vector Add Double (VFP)

Reference

View in Arm A64 ISA Reference ↗ Arm AArch32 ISA

Instruction Forms

Encoding	Instruction	ISA	Bit pattern
0xF2000D00	VADD{<c>}{<q>}.<dt> {<Dd>, }<Dn>, <Dm>	A32	1111001 \| 0 \| 0 \| D \| 0 \| sz \| Vn \| Vd \| 1101 \| N \| 0 \| M \| 0 \| Vm
0xF2000D40	VADD{<c>}{<q>}.<dt> {<Qd>, }<Qn>, <Qm>	A32	1111001 \| 0 \| 0 \| D \| 0 \| sz \| Vn \| Vd \| 1101 \| N \| 1 \| M \| 0 \| Vm
0x0E300900	VADD{<c>}{<q>}.F16 {<Sd>,} <Sn>, <Sm>	A32	cond \| 1110 \| 0 \| D \| 11 \| Vn \| Vd \| 10 \| 01 \| N \| 0 \| M \| 0 \| Vm
0x0E300A00	VADD{<c>}{<q>}.F32 {<Sd>,} <Sn>, <Sm>	A32	cond \| 1110 \| 0 \| D \| 11 \| Vn \| Vd \| 10 \| 10 \| N \| 0 \| M \| 0 \| Vm
0x0E300B00	VADD{<c>}{<q>}.F64 {<Dd>,} <Dn>, <Dm>	A32	cond \| 1110 \| 0 \| D \| 11 \| Vn \| Vd \| 10 \| 11 \| N \| 0 \| M \| 0 \| Vm
0xEF000D00	VADD{<c>}{<q>}.<dt> {<Dd>, }<Dn>, <Dm>	T32	111 \| 0 \| 11110 \| D \| 0 \| sz \| Vn \| Vd \| 1101 \| N \| 0 \| M \| 0 \| Vm
0xEF000D40	VADD{<c>}{<q>}.<dt> {<Qd>, }<Qn>, <Qm>	T32	111 \| 0 \| 11110 \| D \| 0 \| sz \| Vn \| Vd \| 1101 \| N \| 1 \| M \| 0 \| Vm
0xEE300900	VADD{<c>}{<q>}.F16 {<Sd>,} <Sn>, <Sm>	T32	11101110 \| 0 \| D \| 11 \| Vn \| Vd \| 10 \| 01 \| N \| 0 \| M \| 0 \| Vm
0xEE300A00	VADD{<c>}{<q>}.F32 {<Sd>,} <Sn>, <Sm>	T32	11101110 \| 0 \| D \| 11 \| Vn \| Vd \| 10 \| 10 \| N \| 0 \| M \| 0 \| Vm
0xEE300B00	VADD{<c>}{<q>}.F64 {<Dd>,} <Dn>, <Dm>	T32	11101110 \| 0 \| D \| 11 \| Vn \| Vd \| 10 \| 11 \| N \| 0 \| M \| 0 \| Vm
0xF2000800	VADD{<c>}{<q>}.<dt> {<Dd>, }<Dn>, <Dm>	A32	1111001 \| 0 \| 0 \| D \| size \| Vn \| Vd \| 1000 \| N \| 0 \| M \| 0 \| Vm
0xF2000840	VADD{<c>}{<q>}.<dt> {<Qd>, }<Qn>, <Qm>	A32	1111001 \| 0 \| 0 \| D \| size \| Vn \| Vd \| 1000 \| N \| 1 \| M \| 0 \| Vm
0xEF000800	VADD{<c>}{<q>}.<dt> {<Dd>, }<Dn>, <Dm>	T32	111 \| 0 \| 11110 \| D \| size \| Vn \| Vd \| 1000 \| N \| 0 \| M \| 0 \| Vm
0xEF000840	VADD{<c>}{<q>}.<dt> {<Qd>, }<Qn>, <Qm>	T32	111 \| 0 \| 11110 \| D \| size \| Vn \| Vd \| 1000 \| N \| 1 \| M \| 0 \| Vm

Description

Vector Add (integer) adds corresponding elements in two vectors, and places the results in the destination vector. Depending on settings in the CPACR, NSACR, and HCPTR registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be undefined, or trapped to Hyp mode. For more information see Enabling Advanced SIMD and floating-point support.

Operation

if ConditionPassed() then
    EncodingSpecificOperations();  CheckAdvSIMDEnabled();
    for r = 0 to regs-1
        for e = 0 to elements-1
            Elem[D[d+r],e,esize] = Elem[D[n+r],e,esize] + Elem[D[m+r],e,esize];