vcmp

Vector Compare (VFP)

VCMP<c>.F32 <Sd>, <Sm>

Compares two floating-point values.

Pseudocode Operation

result ← compare(Sd, Sm)
FPSCR.N ← result.N
FPSCR.Z ← result.Z
FPSCR.C ← result.C
FPSCR.V ← result.V

Example

VCMP.F32 s0, s2

Encoding

Binary Layout
cond
31:28
11101
27:23
D
22
11
21:20
0
19
100
18:16
Vd
15:12
10
11:10
10
9:8
0
7
1
6
M
5
0
4
Vm
3:0
 
Format VFP Compare
Opcode 0x0EB40A40
Extension VFP (Float)

Operands

  • Sd
    Destination 32-bit floating-point register
  • Sm
    Second source 32-bit floating-point register

Related

Other forms of vcmp

  • vcmp Vector Compare Zero (VFP)
  • vcmp Vector Compare (Double)

More in VFP (Float)

Reference

View in Arm A64 ISA Reference ↗ Arm AArch32 ISA

Instruction Forms

Encoding Instruction ISA Bit pattern
0x0EB40940 VCMP{<c>}{<q>}.F16 <Sd>, <Sm> A32 cond | 11101 | D | 11 | 0 | 100 | Vd | 10 | 01 | 0 | 1 | M | 0 | Vm
0x0EB40A40 VCMP{<c>}{<q>}.F32 <Sd>, <Sm> A32 cond | 11101 | D | 11 | 0 | 100 | Vd | 10 | 10 | 0 | 1 | M | 0 | Vm
0x0EB40B40 VCMP{<c>}{<q>}.F64 <Dd>, <Dm> A32 cond | 11101 | D | 11 | 0 | 100 | Vd | 10 | 11 | 0 | 1 | M | 0 | Vm
0x0EB50940 VCMP{<c>}{<q>}.F16 <Sd>, #0.0 A32 cond | 11101 | D | 11 | 0 | 101 | Vd | 10 | 01 | 0 | 1 | 0 | 0 | 0000
0x0EB50A40 VCMP{<c>}{<q>}.F32 <Sd>, #0.0 A32 cond | 11101 | D | 11 | 0 | 101 | Vd | 10 | 10 | 0 | 1 | 0 | 0 | 0000
0x0EB50B40 VCMP{<c>}{<q>}.F64 <Dd>, #0.0 A32 cond | 11101 | D | 11 | 0 | 101 | Vd | 10 | 11 | 0 | 1 | 0 | 0 | 0000
0xEEB40940 VCMP{<c>}{<q>}.F16 <Sd>, <Sm> T32 111011101 | D | 11 | 0 | 100 | Vd | 10 | 01 | 0 | 1 | M | 0 | Vm
0xEEB40A40 VCMP{<c>}{<q>}.F32 <Sd>, <Sm> T32 111011101 | D | 11 | 0 | 100 | Vd | 10 | 10 | 0 | 1 | M | 0 | Vm
0xEEB40B40 VCMP{<c>}{<q>}.F64 <Dd>, <Dm> T32 111011101 | D | 11 | 0 | 100 | Vd | 10 | 11 | 0 | 1 | M | 0 | Vm
0xEEB50940 VCMP{<c>}{<q>}.F16 <Sd>, #0.0 T32 111011101 | D | 11 | 0 | 101 | Vd | 10 | 01 | 0 | 1 | 0 | 0 | 0000
0xEEB50A40 VCMP{<c>}{<q>}.F32 <Sd>, #0.0 T32 111011101 | D | 11 | 0 | 101 | Vd | 10 | 10 | 0 | 1 | 0 | 0 | 0000
0xEEB50B40 VCMP{<c>}{<q>}.F64 <Dd>, #0.0 T32 111011101 | D | 11 | 0 | 101 | Vd | 10 | 11 | 0 | 1 | 0 | 0 | 0000

Description

Vector Compare compares two floating-point registers, or one floating-point register and zero. It writes the result to the FPSCR flags. These are normally transferred to the PSTATE.{N, Z, C, V} Condition flags by a subsequent VMRS instruction. This instruction raises an Invalid Operation floating-point exception if either or both of the operands is a signaling NaN. Depending on settings in the CPACR, NSACR, and HCPTR registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be undefined, or trapped to Hyp mode. For more information see Enabling Advanced SIMD and floating-point support.

Operation

if ConditionPassed() then
    EncodingSpecificOperations();  CheckVFPEnabled(TRUE);
    bits(4) nzcv;
    case esize of
        when 16
            bits(16) op16 = if with_zero then FPZero('0', 16) else S[m]<15:0>;
            nzcv = FPCompare(S[d]<15:0>, op16, quiet_nan_exc, FPSCR[]);
        when 32
            bits(32) op32 = if with_zero then FPZero('0', 32) else S[m];
            nzcv = FPCompare(S[d], op32, quiet_nan_exc, FPSCR[]);
        when 64
            bits(64) op64 = if with_zero then FPZero('0', 64) else D[m];
            nzcv = FPCompare(D[d], op64, quiet_nan_exc, FPSCR[]);

    FPSCR<31:28> = nzcv; // FPSCR.<N,Z,C,V> set to nzcv