vfma

Vector Fused Multiply Accumulate (Double)

VFMA<c>.F64 <Qd>, <Qn>, <Qm>

Fused multiply-add (Double).

Details

Performs a fused multiply-accumulate operation on two double-precision values with a third double-precision accumulator value: Qd ← Qd + (Qn × Qm). The operation is a single fused operation with one rounding step, providing higher precision than separate multiply and add instructions. FPSCR exception flags may be set. Requires VFPv4 extension and executes only in A32 instruction set.

Pseudocode Operation

Qd ← Qd + (Qn × Qm)
FPSCR.IOC ← 1 if invalid operand
FPSCR.UFC ← 1 if result underflows
FPSCR.OFC ← 1 if result overflows
FPSCR.IXC ← 1 if result is inexact

Example

VFMA.F64 q0, q1, q2

Encoding

Binary Layout
cond
1110
1
D
10
Vn
Vd
10
11
N
0
M
0
Vm
 
Format VFP Arith
Opcode 0x0EA00B00
Extension VFPv4 (Float)

Operands

  • Qd
    Destination 128-bit SIMD register
  • Qn
    First source 128-bit SIMD register
  • Qm
    Second source 128-bit SIMD register

Reference (Arm AArch32 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0xF2000C10 VFMA{<c>}{<q>}.<dt> <Dd>, <Dn>, <Dm> A32 1111001 | 0 | 0 | D | 0 | sz | Vn | Vd | 1100 | N | 0 | M | 1 | Vm
0xF2000C50 VFMA{<c>}{<q>}.<dt> <Qd>, <Qn>, <Qm> A32 1111001 | 0 | 0 | D | 0 | sz | Vn | Vd | 1100 | N | 1 | M | 1 | Vm
0x0EA00900 VFMA{<c>}{<q>}.F16 <Sd>, <Sn>, <Sm> A32 cond | 1110 | 1 | D | 10 | Vn | Vd | 10 | 01 | N | 0 | M | 0 | Vm
0x0EA00A00 VFMA{<c>}{<q>}.F32 <Sd>, <Sn>, <Sm> A32 cond | 1110 | 1 | D | 10 | Vn | Vd | 10 | 10 | N | 0 | M | 0 | Vm
0x0EA00B00 VFMA{<c>}{<q>}.F64 <Dd>, <Dn>, <Dm> A32 cond | 1110 | 1 | D | 10 | Vn | Vd | 10 | 11 | N | 0 | M | 0 | Vm
0xEF000C10 VFMA{<c>}{<q>}.<dt> <Dd>, <Dn>, <Dm> T32 111 | 0 | 11110 | D | 0 | sz | Vn | Vd | 1100 | N | 0 | M | 1 | Vm
0xEF000C50 VFMA{<c>}{<q>}.<dt> <Qd>, <Qn>, <Qm> T32 111 | 0 | 11110 | D | 0 | sz | Vn | Vd | 1100 | N | 1 | M | 1 | Vm
0xEEA00900 VFMA{<c>}{<q>}.F16 <Sd>, <Sn>, <Sm> T32 11101110 | 1 | D | 10 | Vn | Vd | 10 | 01 | N | 0 | M | 0 | Vm
0xEEA00A00 VFMA{<c>}{<q>}.F32 <Sd>, <Sn>, <Sm> T32 11101110 | 1 | D | 10 | Vn | Vd | 10 | 10 | N | 0 | M | 0 | Vm
0xEEA00B00 VFMA{<c>}{<q>}.F64 <Dd>, <Dn>, <Dm> T32 11101110 | 1 | D | 10 | Vn | Vd | 10 | 11 | N | 0 | M | 0 | Vm
0xFC300810 VFMA<bt>{<q>}.BF16 <Qd>, <Qn>, <Qm> A32 1111110 | 00 | D | 11 | Vn | Vd | 1 | 0 | 0 | 0 | N | Q | M | 1 | Vm
0xFE300810 VFMA<bt>{<q>}.BF16 <Qd>, <Qn>, <Dm>[<index>] A32 11111110 | 0 | D | 11 | Vn | Vd | 1000 | N | Q | M | 1 | Vm

Description

Vector Fused Multiply Accumulate multiplies corresponding elements of two vectors, and accumulates the results into the elements of the destination vector. The instruction does not round the result of the multiply before the accumulation. Depending on settings in the CPACR, NSACR, HCPTR, and FPEXC registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be undefined, or trapped to Hyp mode. For more information see Enabling Advanced SIMD and floating-point support.

Operation

if ConditionPassed() then
    EncodingSpecificOperations();  CheckAdvSIMDOrVFPEnabled(TRUE, advsimd);
    if advsimd then // Advanced SIMD instruction
        for r = 0 to regs-1
            for e = 0 to elements-1
                bits(esize) op1 = Elem[D[n+r],e,esize];
                if op1_neg then op1 = FPNeg(op1);
                Elem[D[d+r],e,esize] = FPMulAdd(Elem[D[d+r],e,esize],
                                       op1, Elem[D[m+r],e,esize], StandardFPSCRValue());

    else // VFP instruction
        case esize of
            when 16
                op16 = if op1_neg then FPNeg(S[n]<15:0>) else S[n]<15:0>;
                S[d] = Zeros(16) : FPMulAdd(S[d]<15:0>, op16, S[m]<15:0>, FPSCR[]);
            when 32
                op32 = if op1_neg then FPNeg(S[n]) else S[n];
                S[d] = FPMulAdd(S[d], op32, S[m], FPSCR[]);
            when 64
                op64 = if op1_neg then FPNeg(D[n]) else D[n];
                D[d] = FPMulAdd(D[d], op64, D[m], FPSCR[]);