dup

SVE Duplicate Scalar

DUP <Zd>.<T>, <R><n|m>

Broadcasts a scalar register or immediate to all active vector elements.

Details

Broadcasts a scalar value from a general-purpose register to all elements of a vector. The destination register Zd is set to replicate the source scalar across all elements of type T without predication. No flags are affected. This is an AArch64-only SVE instruction.

Pseudocode Operation

for i = 0 to VL/esize-1
  Zd[i] ← Rn

Example

DUP z0.s.T, Rn

Encoding

Binary Layout
00000101
size
100000001110
Rn
Zd
 
Format SVE Move
Opcode 0x05203800
Extension SVE

Operands

  • Zd
    Destination scalable vector register (SVE)
  • Rn
    Source GPR

Reference (Arm A64 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0x5E000400 DUP <V><d>, <Vn>.<T>[<index>] A64 01 | 0 | 11110000 | imm5 | 0 | 0000 | 1 | Rn | Rd
0x0E000400 DUP <Vd>.<T>, <Vn>.<Ts>[<index>] A64 0 | Q | 0 | 01110000 | imm5 | 0 | 0000 | 1 | Rn | Rd
0x0E000C00 DUP <Vd>.<T>, <R><n> A64 0 | Q | 0 | 01110000 | imm5 | 0 | 0001 | 1 | Rn | Rd
0x2538C000 DUP <Zd>.<T>, #<imm>{, <shift>} A64 00100101 | size | 111 | 0 | 0 | 011 | sh | imm8 | Zd
0x05203800 DUP <Zd>.<T>, <R><n|SP> A64 00000101 | size | 100000001110 | Rn | Zd
0x05202000 DUP <Zd>.<T>, <Zn>.<T>[<imm>] A64 00000101 | imm2 | 1 | tsz | 001000 | Zn | Zd

Description

Unconditionally broadcast the general-purpose scalar source register into each element of the destination vector. This instruction is unpredicated.

Operation

CheckSVEEnabled();
constant integer VL = CurrentVL;
constant integer elements = VL DIV esize;
constant integer PL = VL DIV 8;
bits(64) operand;
if n == 31 then
    operand = SP[];
else
    operand = X[n, 64];
bits(VL) result;

for e = 0 to elements-1
    Elem[result, e, esize] = operand<esize-1:0>;

Z[d, VL] = result;