umax

SVE Unsigned Maximum

UMAX <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>

Determines maximum unsigned value per element.

Pseudocode Operation

for e = 0 to VL/getElementSize(T)-1
  if Pg[e] == 1 then
    Zdn[e] ← max_unsigned(Zdn[e], Zm[e])
  end if
end for

Example

UMAX z0.s.T, p0/m/M, z0.s.T, z2.s.T

Encoding

Binary Layout

00000100

31:24

size

23:22

001

21:19

0

18

0

17

1

16

000

15:13

Pg

12:10

Zm

9:5

Zdn

4:0

 

Format SVE Integer Binary

Opcode 0x04090000

Extension SVE

Operands

• Zdn
  Combined destination/source scalable vector register (SVE)
• Pg
  Mask
• Zm
  Second source scalable vector register (SVE)

Related

Other forms of umax

• umax Vector Unsigned Maximum

More in SVE

Reference

View in Arm A64 ISA Reference ↗ Arm A64 ISA

Instruction Forms

Encoding	Instruction		ISA		Bit pattern
0x2E206400	UMAX <Vd>.<T>, <Vn>.<T>, <Vm>.<T>		A64		0 | Q | 1 | 01110 | size | 1 | Rm | 0110 | 0 | 1 | Rn | Rd
0x11C40000	UMAX <Wd>, <Wn>, #<uimm>		A64		0 | 0 | 0 | 1000111 | 0001 | imm8 | Rn | Rd
0x91C40000	UMAX <Xd>, <Xn>, #<uimm>		A64		1 | 0 | 0 | 1000111 | 0001 | imm8 | Rn | Rd
0xC120A001	UMAX { <Zdn1>.<T>-<Zdn2>.<T> }, { <Zdn1>.<T>-<Zdn2>.<T> }, <Zm>.<T>		A64		11000001 | size | 10 | Zm | 101000 | 0000 | 0 | Zdn | 1
0xC120A801	UMAX { <Zdn1>.<T>-<Zdn4>.<T> }, { <Zdn1>.<T>-<Zdn4>.<T> }, <Zm>.<T>		A64		11000001 | size | 10 | Zm | 101010 | 0000 | 0 | Zdn | 0 | 1
0xC120B001	UMAX { <Zdn1>.<T>-<Zdn2>.<T> }, { <Zdn1>.<T>-<Zdn2>.<T> }, { <Zm1>.<T>-<Zm2>.<T> }		A64		11000001 | size | 1 | Zm | 0101100 | 000 | 0 | 0 | Zdn | 1
0xC120B801	UMAX { <Zdn1>.<T>-<Zdn4>.<T> }, { <Zdn1>.<T>-<Zdn4>.<T> }, { <Zm1>.<T>-<Zm4>.<T> }		A64		11000001 | size | 1 | Zm | 00101110 | 000 | 0 | 0 | Zdn | 0 | 1
0x1AC06400	UMAX <Wd>, <Wn>, <Wm>		A64		0 | 0 | 0 | 11010110 | Rm | 011001 | Rn | Rd
0x9AC06400	UMAX <Xd>, <Xn>, <Xm>		A64		1 | 0 | 0 | 11010110 | Rm | 011001 | Rn | Rd
0x04090000	UMAX <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>		A64		00000100 | size | 001 | 0 | 0 | 1 | 000 | Pg | Zm | Zdn
0x2529C000	UMAX <Zdn>.<T>, <Zdn>.<T>, #<imm>		A64		00100101 | size | 101 | 00 | 1 | 11 | 0 | imm8 | Zdn

Description

Determine the unsigned maximum of active elements of the second source vector and corresponding elements of the first source vector and destructively place the results in the corresponding elements of the first source vector. Inactive elements in the destination vector register remain unmodified.

Operation

CheckSVEEnabled();
constant integer VL = CurrentVL;
constant integer PL = VL DIV 8;
constant integer elements = VL DIV esize;
bits(PL) mask = P[g, PL];
bits(VL) operand1 = Z[dn, VL];
bits(VL) operand2 = if AnyActiveElement(mask, esize) then Z[m, VL] else Zeros(VL);
bits(VL) result;

for e = 0 to elements-1
    integer element1 = Int(Elem[operand1, e, esize], unsigned);
    integer element2 = Int(Elem[operand2, e, esize], unsigned);
    if ActivePredicateElement(mask, e, esize) then
        integer maximum = Max(element1, element2);
        Elem[result, e, esize] = maximum<esize-1:0>;
    else
        Elem[result, e, esize] = Elem[operand1, e, esize];

Z[dn, VL] = result;