pop.w

Pop (Wide)

POP.W <registers>

Thumb-2 32-bit Pop.

Pseudocode Operation

for i = 0 to 15
  if registers[i] == 1 then
    Ri ← memory[SP]
    SP ← SP + 4
if registers[15] == 1 then
  PC ← R15

Example

POP.W registers

Encoding

Binary Layout

1110100

31:25

01

24:23

0

22

1

21

1

20

1101

19:16

P

15

M

14

register_list

13:0

 

Format Thumb Load Multiple

Opcode 0xE8BD0000

Extension T32 (Thumb2)

Operands

• registers
  List

Related

More in T32 (Thumb2)

Reference

View in Arm A64 ISA Reference ↗ Arm AArch32 ISA

Instruction Forms

Encoding	Instruction		ISA		Bit pattern
0xBC00	POP{<c>}{<q>} <registers>		T32		1011 | 1 | 10 | P | register_list
0x08BD0000	POP{<c>}{<q>} <registers>		A32		cond | 100 | 0 | 1 | 0 | 1 | 1 | 1101 | register_list
0xE8BD0000	POP{<c>}.W <registers>		T32		1110100 | 01 | 0 | 1 | 1 | 1101 | P | M | register_list
0x049D0004	POP{<c>}{<q>} <single_register_list>		A32		cond | 010 | 0 | 1 | 0 | 0 | 1 | 1101 | Rt | 000000000100
0xF85D0B04	POP{<c>}{<q>} <single_register_list>		T32		111110000 | 10 | 1 | 1101 | Rt | 1 | 0 | 1 | 1 | 00000100

Description

Loads multiple general-purpose registers from the stack, loading from consecutive memory locations starting at the address in SP, and updates SP to point just above the loaded data