ldc2
Load Coprocessor 2 (A32)
LDC2{L}<c> <coproc>, <CRd>, [<Rn>, #+/-<imm>]{!}
Loads memory into a coprocessor (Extension encoding).
Details
Load Coprocessor 2 (unconditional extension): loads a word or multiple words from memory into a coprocessor register, with the memory address computed from Rn plus an optional offset. The P, U, W bits control pre/post-indexing and writeback; the instruction is unconditional and uses the extension encoding. Restricted to privileged execution states and requires a coprocessor.
Pseudocode Operation
if P == 0 and W == 1 then
address ← Rn
Rn ← Rn + (if U then imm8 << 2 else -(imm8 << 2))
else if P == 1 then
address ← Rn + (if U then imm8 << 2 else -(imm8 << 2))
if W == 1 then Rn ← address
Coprocessor[coproc].LoadFromMemory(CRd, address)Example
LDC2 p15, c0, [r1, #+/-#16]!
Encoding
Binary Layout
1111110
P
U
N
W
1
Rn
CRd
coproc
imm8
Operands
-
coproc
CP Num -
CRd
Destination coprocessor register -
Rn
First source / base general-purpose register