vbfmmla

Vector BFloat16 Matrix Multiply (A32)

VBFMMLA<c>.BF16 <Qd>, <Qn>, <Qm>

BFloat16 matrix multiply-accumulate.

Details

Multiplies two 128-bit SIMD registers containing BFloat16 (16-bit brain floating-point) elements in 2×2 matrix format and accumulates the result into the destination register. Each 2×2 matrix multiplication processes four BFloat16 values, producing single-precision results that are accumulated. Condition flags (N, Z, C, V) are unaffected. This instruction requires the NEON BFloat16 extension and executes in A32 (ARM) instruction set only.

Pseudocode Operation

for i = 0 to 3 do
  // Extract 2x2 BF16 matrix from Qn
  matrix_a[0] = BF16_to_F32(Qn[i*2*16 + 0:15])
  matrix_a[1] = BF16_to_F32(Qn[i*2*16 + 16:31])
  matrix_a[2] = BF16_to_F32(Qn[i*2*16 + 32:47])
  matrix_a[3] = BF16_to_F32(Qn[i*2*16 + 48:63])
  // Extract 2x2 BF16 matrix from Qm
  matrix_b[0] = BF16_to_F32(Qm[i*2*16 + 0:15])
  matrix_b[1] = BF16_to_F32(Qm[i*2*16 + 16:31])
  matrix_b[2] = BF16_to_F32(Qm[i*2*16 + 32:47])
  matrix_b[3] = BF16_to_F32(Qm[i*2*16 + 48:63])
  // Multiply and accumulate
  Qd[i*32 + 0:31] = Qd[i*32 + 0:31] + matrix_a[0] * matrix_b[0] + matrix_a[1] * matrix_b[2]
  Qd[i*32 + 32:63] = Qd[i*32 + 32:63] + matrix_a[2] * matrix_b[0] + matrix_a[3] * matrix_b[2]

Example

VBFMMLA.BF16 q0, q1, q2

Encoding

Binary Layout
11111100
0
0
11
Vn
Vd
1100
N
Q
M
1
Vm
 
Format NEON BFloat16
Opcode 0xFC000C40
Extension NEON (BFloat16)

Operands

  • Qd
    Destination 128-bit SIMD register
  • Qn
    First source 128-bit SIMD register
  • Qm
    Second source 128-bit SIMD register