vcvtt

Vector Convert Half-Precision (Top)

VCVTT<c>.F16.F32 <Sd>, <Sm>

Converts single-precision to half-precision (Top half).

Pseudocode Operation

Sd[31:16] ← ConvertToHalf(Sm); Sd[15:0] unchanged

Example

VCVTT.F16.F32 s0, s2

Encoding

Binary Layout
cond
31:28
11101
27:23
D
22
11
21:20
0
19
01
18:17
0
16
Vd
15:12
10
11:10
1
9
0
8
1
7
1
6
M
5
0
4
Vm
3:0
 
Format VFP Convert
Opcode 0x0EB20AC0
Extension VFP (Half)

Operands

  • Sd
    Dest (Half)
  • Sm
    Src (Single)

Related

More in VFP (Half)

Reference

View in Arm A64 ISA Reference ↗ Arm AArch32 ISA

Instruction Forms

Encoding Instruction ISA Bit pattern
0x0EB20AC0 VCVTT{<c>}{<q>}.F32.F16 <Sd>, <Sm> A32 cond | 11101 | D | 11 | 0 | 01 | 0 | Vd | 10 | 1 | 0 | 1 | 1 | M | 0 | Vm
0x0EB20BC0 VCVTT{<c>}{<q>}.F64.F16 <Dd>, <Sm> A32 cond | 11101 | D | 11 | 0 | 01 | 0 | Vd | 10 | 1 | 1 | 1 | 1 | M | 0 | Vm
0x0EB30AC0 VCVTT{<c>}{<q>}.F16.F32 <Sd>, <Sm> A32 cond | 11101 | D | 11 | 0 | 01 | 1 | Vd | 10 | 1 | 0 | 1 | 1 | M | 0 | Vm
0x0EB30BC0 VCVTT{<c>}{<q>}.F16.F64 <Sd>, <Dm> A32 cond | 11101 | D | 11 | 0 | 01 | 1 | Vd | 10 | 1 | 1 | 1 | 1 | M | 0 | Vm
0xEEB20AC0 VCVTT{<c>}{<q>}.F32.F16 <Sd>, <Sm> T32 111011101 | D | 11 | 0 | 01 | 0 | Vd | 10 | 1 | 0 | 1 | 1 | M | 0 | Vm
0xEEB20BC0 VCVTT{<c>}{<q>}.F64.F16 <Dd>, <Sm> T32 111011101 | D | 11 | 0 | 01 | 0 | Vd | 10 | 1 | 1 | 1 | 1 | M | 0 | Vm
0xEEB30AC0 VCVTT{<c>}{<q>}.F16.F32 <Sd>, <Sm> T32 111011101 | D | 11 | 0 | 01 | 1 | Vd | 10 | 1 | 0 | 1 | 1 | M | 0 | Vm
0xEEB30BC0 VCVTT{<c>}{<q>}.F16.F64 <Sd>, <Dm> T32 111011101 | D | 11 | 0 | 01 | 1 | Vd | 10 | 1 | 1 | 1 | 1 | M | 0 | Vm
0x0EB309C0 VCVTT{<c>}{<q>}.BF16.F32 <Sd>, <Sm> A32 cond | 11101 | D | 11 | 0 | 011 | Vd | 10 | 01 | 1 | 1 | M | 0 | Vm
0xEEB309C0 VCVTT{<c>}{<q>}.BF16.F32 <Sd>, <Sm> T32 111011101 | D | 11 | 0 | 011 | Vd | 10 | 01 | 1 | 1 | M | 0 | Vm

Description

Convert to or from a half-precision value in the top half of a single-precision register does one of the following: Depending on settings in the CPACR, NSACR, HCPTR, and FPEXC registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be undefined, or trapped to Hyp mode. For more information see Enabling Advanced SIMD and floating-point support.

Operation

if ConditionPassed() then
    EncodingSpecificOperations(); CheckVFPEnabled(TRUE);
    bits(16) hp;
    if convert_from_half then
        hp = S[m]<lowbit+15:lowbit>;
        if uses_double then
            D[d] = FPConvert(hp, FPSCR[], 64);
        else
            S[d] = FPConvert(hp, FPSCR[], 32);
    else
        if uses_double then
            hp = FPConvert(D[m], FPSCR[], 16);
        else
            hp = FPConvert(S[m], FPSCR[], 16);
        S[d]<lowbit+15:lowbit> = hp;