lsr

Logical Shift Right (Register)

LSRV <Wd>, <Wn>, <Wm>

Shifts register right by variable amount.

Pseudocode Operation

shift_amount ← Wm[4:0]
Wd ← Wn >> shift_amount

Example

LSRV w0, w1, w2

Encoding

Binary Layout

11010110

28:21

20:16

0010

15:12

11:10

9:5

4:0

Format Data Processing

Opcode 0x1AC02400

Extension Base

Operands

Wd
Destination 32-bit integer register
Wn
First source / base 32-bit integer register
Wm
Shift Reg

Other forms of lsr

lsr SVE Logical Shift Right (Predicated)
lsr Logical Shift Right (A32)

Reference

View in Arm A64 ISA Reference ↗ Arm A64 ISA

Instruction Forms

Encoding	Instruction	ISA	Bit pattern
0x1AC02400	LSR <Wd>, <Wn>, <Wm>	A64	0 \| 0 \| 0 \| 11010110 \| Rm \| 0010 \| 01 \| Rn \| Rd
0x9AC02400	LSR <Xd>, <Xn>, <Xm>	A64	1 \| 0 \| 0 \| 11010110 \| Rm \| 0010 \| 01 \| Rn \| Rd
0x53007C00	LSR <Wd>, <Wn>, #<shift>	A64	0 \| 10 \| 100110 \| 0 \| immr \| 011111 \| Rn \| Rd
0xD340FC00	LSR <Xd>, <Xn>, #<shift>	A64	1 \| 10 \| 100110 \| 1 \| immr \| 111111 \| Rn \| Rd
0x04018000	LSR <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, #<const>	A64	00000100 \| tszh \| 00 \| 0 \| 0 \| 0 \| 1 \| 100 \| Pg \| tszl \| imm3 \| Zdn
0x04198000	LSR <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.D	A64	00000100 \| size \| 011 \| 0 \| 0 \| 1 \| 100 \| Pg \| Zm \| Zdn
0x04118000	LSR <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>	A64	00000100 \| size \| 010 \| 0 \| 0 \| 1 \| 100 \| Pg \| Zm \| Zdn
0x04209400	LSR <Zd>.<T>, <Zn>.<T>, #<const>	A64	00000100 \| tszh \| 1 \| tszl \| imm3 \| 1001 \| 0 \| 1 \| Zn \| Zd
0x04208400	LSR <Zd>.<T>, <Zn>.<T>, <Zm>.D	A64	00000100 \| size \| 1 \| Zm \| 1000 \| 0 \| 1 \| Zn \| Zd

Description

Logical Shift Right (register) shifts a register value right by a variable number of bits, shifting in zeros, and writes the result to the destination register. The remainder obtained by dividing the second source register by the data size defines the number of bits by which the first source register is right-shifted.

lsr