orr

Vector Bitwise OR

ORR <Vd>.<T>, <Vn>.<T>, <Vm>.<T>

Bitwise OR of two vectors.

Details

Performs bitwise OR between corresponding elements of Vn and Vm, storing results in Vd. Operates on the full vector width without regard to element size. The Q bit determines operation width (64-bit for Q=0, 128-bit for Q=1). No condition flags are affected. AArch64 NEON extension.

Pseudocode Operation

for i = 0 to (128 >> (if Q then 0 else 1)) - 1:
  Vd[i] ← Vn[i] OR Vm[i];

Example

ORR v0.4s.T, v1.4s.T, v2.4s.T

Encoding

Binary Layout
0
Q
0
01110
10
1
Rm
00011
1
Rn
Rd
 
Format SIMD Three Register
Opcode 0x0EA01C00
Extension NEON (SIMD)

Operands

  • Vd
    Destination SIMD/FP vector register
  • Vn
    First source SIMD/FP vector register
  • Vm
    Second source SIMD/FP vector register

Reference (Arm A64 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0x0F009400 ORR <Vd>.<T>, #<imm8>{, LSL #<amount>} A64 0 | Q | 0 | 0111100000 | a | b | c | cmode | 0 | 1 | d | e | f | g | h | Rd
0x0F001400 ORR <Vd>.<T>, #<imm8>{, LSL #<amount>} A64 0 | Q | 0 | 0111100000 | a | b | c | cmode | 0 | 1 | d | e | f | g | h | Rd
0x0EA01C00 ORR <Vd>.<T>, <Vn>.<T>, <Vm>.<T> A64 0 | Q | 0 | 01110 | 10 | 1 | Rm | 00011 | 1 | Rn | Rd
0x32000000 ORR <Wd|WSP>, <Wn>, #<imm> A64 0 | 01 | 100100 | 0 | immr | imms | Rn | Rd
0xB2000000 ORR <Xd|SP>, <Xn>, #<imm> A64 1 | 01 | 100100 | N | immr | imms | Rn | Rd
0x2A000000 ORR <Wd>, <Wn>, <Wm>{, <shift> #<amount>} A64 0 | 01 | 01010 | shift | 0 | Rm | imm6 | Rn | Rd
0xAA000000 ORR <Xd>, <Xn>, <Xm>{, <shift> #<amount>} A64 1 | 01 | 01010 | shift | 0 | Rm | imm6 | Rn | Rd
0x25804000 ORR <Pd>.B, <Pg>/Z, <Pn>.B, <Pm>.B A64 00100101 | 1 | 0 | 00 | Pm | 01 | Pg | 0 | Pn | 0 | Pd
0x04180000 ORR <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> A64 00000100 | size | 011 | 00 | 0 | 000 | Pg | Zm | Zdn
0x05000000 ORR <Zdn>.<T>, <Zdn>.<T>, #<const> A64 00000101 | 0 | 0 | 0000 | imm13 | Zdn
0x04603000 ORR <Zd>.D, <Zn>.D, <Zm>.D A64 00000100 | 0 | 1 | 1 | Zm | 001100 | Zn | Zd

Description

Bitwise inclusive OR (vector, register). This instruction performs a bitwise OR between the two source SIMD&FP registers, and writes the result to the destination SIMD&FP register. Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = V[n, datasize];
bits(datasize) operand2 = V[m, datasize];
bits(datasize) result;


result = operand1 OR operand2;

V[d, datasize] = result;