msub

Multiply-Subtract

MSUB <Wd>, <Wn>, <Wm>, <Wa>

Calculates (Ra - (Rn * Rm)).

Pseudocode Operation

temp ← Wa - (Wn × Wm)
Wd ← temp[31:0]

Example

MSUB w0, w1, w2, w5

Encoding

Binary Layout

0

31

00

30:29

11011

28:24

000

23:21

Rm

20:16

1

15

Ra

14:10

Rn

9:5

Rd

4:0

 

Format Data Processing

Opcode 0x1B008000

Extension Base

Operands

• Wd
  Destination 32-bit integer register
• Wn
  First source / base 32-bit integer register
• Wm
  Second source / offset 32-bit integer register
• Wa
  Minuend

Related

More in Base

Reference

View in Arm A64 ISA Reference ↗ Arm A64 ISA

Instruction Forms

Encoding	Instruction		ISA		Bit pattern
0x1B008000	MSUB <Wd>, <Wn>, <Wm>, <Wa>		A64		0 | 00 | 11011 | 000 | Rm | 1 | Ra | Rn | Rd
0x9B008000	MSUB <Xd>, <Xn>, <Xm>, <Xa>		A64		1 | 00 | 11011 | 000 | Rm | 1 | Ra | Rn | Rd

Description

Multiply-Subtract multiplies two register values, subtracts the product from a third register value, and writes the result to the destination register.

Operation

bits(destsize) operand1 = X[n, destsize];
bits(destsize) operand2 = X[m, destsize];
bits(destsize) operand3 = X[a, destsize];

integer result;

result = UInt(operand3) - (UInt(operand1) * UInt(operand2));
X[d, destsize] = result<destsize-1:0>;