lsl

Logical Shift Left (Register)

LSLV <Wd>, <Wn>, <Wm>

Shifts register left by variable amount.

Pseudocode Operation

shift_amount ← Wm[4:0]
Wd ← Wn << shift_amount

Example

LSLV w0, w1, w2

Encoding

Binary Layout

11010110

28:21

20:16

0010

15:12

11:10

9:5

4:0

Format Data Processing

Opcode 0x1AC02000

Extension Base

Operands

Wd
Destination 32-bit integer register
Wn
First source / base 32-bit integer register
Wm
Shift Reg

Other forms of lsl

lsl SVE Shift Left (Predicated)
lsl Logical Shift Left (A32)

Across architectures

Logical and Arithmetic Shift : how x86, ARM, RISC-V, and PowerISA each do this.

Reference

View in Arm A64 ISA Reference ↗ Arm A64 ISA

Instruction Forms

Encoding	Instruction	ISA	Bit pattern
0x1AC02000	LSL <Wd>, <Wn>, <Wm>	A64	0 \| 0 \| 0 \| 11010110 \| Rm \| 0010 \| 00 \| Rn \| Rd
0x9AC02000	LSL <Xd>, <Xn>, <Xm>	A64	1 \| 0 \| 0 \| 11010110 \| Rm \| 0010 \| 00 \| Rn \| Rd
0x53000000	LSL <Wd>, <Wn>, #<shift>	A64	0 \| 10 \| 100110 \| 0 \| immr \| imms \| Rn \| Rd
0xD3400000	LSL <Xd>, <Xn>, #<shift>	A64	1 \| 10 \| 100110 \| 1 \| immr \| imms \| Rn \| Rd
0x04038000	LSL <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, #<const>	A64	00000100 \| tszh \| 00 \| 0 \| 0 \| 1 \| 1 \| 100 \| Pg \| tszl \| imm3 \| Zdn
0x041B8000	LSL <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.D	A64	00000100 \| size \| 011 \| 0 \| 1 \| 1 \| 100 \| Pg \| Zm \| Zdn
0x04138000	LSL <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>	A64	00000100 \| size \| 010 \| 0 \| 1 \| 1 \| 100 \| Pg \| Zm \| Zdn
0x04209C00	LSL <Zd>.<T>, <Zn>.<T>, #<const>	A64	00000100 \| tszh \| 1 \| tszl \| imm3 \| 1001 \| 1 \| 1 \| Zn \| Zd
0x04208C00	LSL <Zd>.<T>, <Zn>.<T>, <Zm>.D	A64	00000100 \| size \| 1 \| Zm \| 1000 \| 1 \| 1 \| Zn \| Zd

Description

Logical Shift Left (register) shifts a register value left by a variable number of bits, shifting in zeros, and writes the result to the destination register. The remainder obtained by dividing the second source register by the data size defines the number of bits by which the first source register is left-shifted.

lsl