st1w

SVE Scatter Store Words (Vector Index)

ST1W { <Zt>.S }, <Pg>, [<Xn|SP>, <Zm>.S, SXTW #<shift>]

Stores words to non-contiguous addresses.

Pseudocode Operation

for i = 0 to VL/32-1
  if Pg[i] == 1
    addr ← Xn + (Zm[i] << shift)
    [addr, 32] ← Zt[i, 32]

Example

ST1W p0/m, [x1, z2.s.S, SXTW #LSL]

Encoding

Binary Layout

1110010

31:25

1

24

0

23

11

22:21

Zm

20:16

1

15

xs

14

0

13

Pg

12:10

Rn

9:5

Zt

4:0

 

Format SVE Scatter

Opcode 0xE5608000

Extension SVE

Operands

• Zt
  Transfer scalable vector register (SVE load/store)
• Pg
  Mask
• Xn
  First source / base 64-bit integer register
• Zm
  Indices

Related

Other forms of st1w

• st1w SVE Store Contiguous Words

More in SVE

Reference

View in Arm A64 ISA Reference ↗ Arm A64 ISA

Instruction Forms

Encoding	Instruction		ISA		Bit pattern
0xA0604000	ST1W { <Zt1>.S-<Zt2>.S }, <PNg>, [<Xn|SP>{, #<imm>, MUL VL}]		A64		101000000110 | imm4 | 0 | 1 | 0 | PNg | Rn | Zt | 0
0xA060C000	ST1W { <Zt1>.S-<Zt4>.S }, <PNg>, [<Xn|SP>{, #<imm>, MUL VL}]		A64		101000000110 | imm4 | 1 | 1 | 0 | PNg | Rn | Zt | 0 | 0
0xA0204000	ST1W { <Zt1>.S-<Zt2>.S }, <PNg>, [<Xn|SP>, <Xm>, LSL #2]		A64		10100000001 | Rm | 0 | 1 | 0 | PNg | Rn | Zt | 0
0xA020C000	ST1W { <Zt1>.S-<Zt4>.S }, <PNg>, [<Xn|SP>, <Xm>, LSL #2]		A64		10100000001 | Rm | 1 | 1 | 0 | PNg | Rn | Zt | 0 | 0
0xA1604000	ST1W { <Zt1>.S, <Zt2>.S }, <PNg>, [<Xn|SP>{, #<imm>, MUL VL}]		A64		101000010110 | imm4 | 0 | 1 | 0 | PNg | Rn | T | 0 | Zt
0xA160C000	ST1W { <Zt1>.S, <Zt2>.S, <Zt3>.S, <Zt4>.S }, <PNg>, [<Xn|SP>{, #<imm>, MUL VL}]		A64		101000010110 | imm4 | 1 | 1 | 0 | PNg | Rn | T | 0 | 0 | Zt
0xA1204000	ST1W { <Zt1>.S, <Zt2>.S }, <PNg>, [<Xn|SP>, <Xm>, LSL #2]		A64		10100001001 | Rm | 0 | 1 | 0 | PNg | Rn | T | 0 | Zt
0xA120C000	ST1W { <Zt1>.S, <Zt2>.S, <Zt3>.S, <Zt4>.S }, <PNg>, [<Xn|SP>, <Xm>, LSL #2]		A64		10100001001 | Rm | 1 | 1 | 0 | PNg | Rn | T | 0 | 0 | Zt
0xE560A000	ST1W { <Zt>.S }, <Pg>, [<Zn>.S{, #<imm>}]		A64		1110010 | 1 | 0 | 11 | imm5 | 101 | Pg | Zn | Zt
0xE540A000	ST1W { <Zt>.D }, <Pg>, [<Zn>.D{, #<imm>}]		A64		1110010 | 1 | 0 | 10 | imm5 | 101 | Pg | Zn | Zt
0xE540E000	ST1W { <Zt>.<T> }, <Pg>, [<Xn|SP>{, #<imm>, MUL VL}]		A64		1110010 | 1 | 0 | 1 | sz | 0 | imm4 | 111 | Pg | Rn | Zt
0xE500E000	ST1W { <Zt>.Q }, <Pg>, [<Xn|SP>{, #<imm>, MUL VL}]		A64		1110010 | 1 | 0 | 00 | 0 | imm4 | 111 | Pg | Rn | Zt
0xE5404000	ST1W { <Zt>.<T> }, <Pg>, [<Xn|SP>, <Xm>, LSL #2]		A64		1110010 | 10 | 1 | sz | Rm | 010 | Pg | Rn | Zt
0xE5004000	ST1W { <Zt>.Q }, <Pg>, [<Xn|SP>, <Xm>, LSL #2]		A64		1110010 | 10 | 0 | 0 | Rm | 010 | Pg | Rn | Zt

Description

Scatter store of words from the active elements of a vector register to the memory addresses generated by a 64-bit scalar base plus vector index. The index values are optionally first sign or zero-extended from 32 to 64 bits and then optionally multiplied by 4. Inactive elements are not written to memory. This instruction is illegal when executed in Streaming SVE mode, unless FEAT_SME_FA64 is implemented and enabled.

Operation

CheckNonStreamingSVEEnabled();
constant integer VL = CurrentVL;
constant integer PL = VL DIV 8;
constant integer elements = VL DIV esize;
bits(64) base;
bits(PL) mask = P[g, PL];
bits(VL) offset;
bits(VL) src;
constant integer mbytes = msize DIV 8;
boolean contiguous = FALSE;
boolean nontemporal = FALSE;
boolean tagchecked = TRUE;
AccessDescriptor accdesc = CreateAccDescSVE(MemOp_STORE, nontemporal, contiguous, tagchecked);

if !AnyActiveElement(mask, esize) then
    if n == 31 && ConstrainUnpredictableBool(Unpredictable_CHECKSPNONEACTIVE) then
        CheckSPAlignment();
else
    if n == 31 then CheckSPAlignment();
    base = if n == 31 then SP[] else X[n, 64];
    offset = Z[m, VL];
    src = Z[t, VL];

for e = 0 to elements-1
    if ActivePredicateElement(mask, e, esize) then
        integer off = Int(Elem[offset, e, esize]<offs_size-1:0>, offs_unsigned);
        bits(64) addr = GenerateAddress(base, off << scale, accdesc);
        Mem[addr, mbytes, accdesc] = Elem[src, e, esize]<msize-1:0>;