incb

SVE Increment Scalar by Byte Count

INCB <Xdn>, <pattern> {, MUL #<imm>}

Increments a general-purpose register by the number of active bytes in the pattern.

Details

Increments a 64-bit general-purpose register by the count of active bytes matching the specified pattern, optionally scaled by an immediate multiplier. The pattern defines which byte positions are considered active (e.g., all bytes, even bytes, etc.). No condition flags are affected. This is an AArch64-only SVE instruction.

Pseudocode Operation

Xdn ← Xdn + (CountActiveBytes(pattern) × (1 + imm4))

Example

INCB Xdn, pattern

Encoding

Binary Layout
00000100
0
0
11
imm4
11100
0
pattern
Rdn
 
Format SVE Inc/Dec
Opcode 0x0430E000
Extension SVE

Operands

  • Xdn
    Register
  • pattern
    Predicate Pattern

Reference (Arm A64 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0x0430E000 INCB <Xdn>{, <pattern>{, MUL #<imm>}} A64 00000100 | 0 | 0 | 11 | imm4 | 11100 | 0 | pattern | Rdn

Description

Determines the number of active elements implied by the named predicate constraint, multiplies that by an immediate in the range 1 to 16 inclusive, and then uses the result to increment the scalar destination. The named predicate constraint limits the number of active elements in a single predicate to: Unspecified or out of range constraint encodings generate an empty predicate or zero element count rather than Undefined Instruction exception.

Operation

CheckSVEEnabled();
integer count = DecodePredCount(pat, esize);
constant integer VL = CurrentVL;
bits(64) operand1 = X[dn, 64];

X[dn, 64] = operand1 + (count * imm);