smuad

Signed Multiply Add Dual

SMUAD{X}<c> <Rd>, <Rn>, <Rm>

Performs two 16x16 multiplies and adds results (Top*Top + Bot*Bot).

Pseudocode Operation

if X then
  prod1 ← SignExtend(Rn[31:16], 32) × SignExtend(Rm[15:0], 32)
  prod2 ← SignExtend(Rn[15:0], 32) × SignExtend(Rm[31:16], 32)
else
  prod1 ← SignExtend(Rn[31:16], 32) × SignExtend(Rm[31:16], 32)
  prod2 ← SignExtend(Rn[15:0], 32) × SignExtend(Rm[15:0], 32)
Rd ← prod1 + prod2

Example

SMUAD r0, r1, r2

Encoding

Binary Layout
cond
31:28
01110
27:23
000
22:20
Rd
19:16
1111
15:12
Rm
11:8
00
7:6
0
5
1
4
Rn
3:0
 
Format Multiply
Opcode 0x0700F010
Extension A32 (DSP)

Operands

  • Rd
    Destination general-purpose register
  • Rn
    First source / base general-purpose register
  • Rm
    Second source / offset general-purpose register

Related

More in A32 (DSP)

Reference

View in Arm A64 ISA Reference ↗ Arm AArch32 ISA

Instruction Forms

Encoding Instruction ISA Bit pattern
0x0700F010 SMUAD{<c>}{<q>} {<Rd>,} <Rn>, <Rm> A32 cond | 01110 | 000 | Rd | 1111 | Rm | 00 | 0 | 1 | Rn
0xFB20F000 SMUAD{<c>}{<q>} {<Rd>,} <Rn>, <Rm> T32 111110110 | 010 | Rn | 1111 | Rd | 00 | 0 | 0 | Rm

Description

Signed Dual Multiply Add performs two signed 16 x 16-bit multiplications. It adds the products together, and writes the result to the destination register. Optionally, the instruction can exchange the halfwords of the second operand before performing the arithmetic. This produces top x bottom and bottom x top multiplication. This instruction sets PSTATE.Q to 1 if the addition overflows. The multiplications cannot overflow.

Operation

if ConditionPassed() then
    EncodingSpecificOperations();
    operand2 = if m_swap then ROR(R[m],16) else R[m];
    product1 = SInt(R[n]<15:0>) * SInt(operand2<15:0>);
    product2 = SInt(R[n]<31:16>) * SInt(operand2<31:16>);
    result = product1 + product2;
    R[d] = result<31:0>;
    if result != SInt(result<31:0>) then  // Signed overflow
        PSTATE.Q = '1';