sub

Subtract (A32)

SUB{S}<c> <Rd>, <Rn>, <Operand2>

Subtracts two values.

Pseudocode Operation

result ← Rn - Operand2;
Rd ← result;
if S then
  N ← result[31];
  Z ← (result == 0);
  C ← NOT(BorrowFrom(Rn - Operand2));
  V ← OverflowFrom(Rn - Operand2);
endif;

Example

SUB r0, r1, r2

Encoding

Binary Layout

cond

31:28

0010

27:24

010

23:21

19:16

15:12

imm12

11:0

Format Data Proc

Opcode 0x02400000

Extension A32 (Base)

Operands

Rd
Destination general-purpose register
Rn
First source / base general-purpose register
Operand2
Flexible second operand (register or shifted register)

Other forms of sub

sub Subtract (Extended Register)
sub Subtract (Immediate)
sub Subtract (Shifted Register)
sub Vector Subtract (Integer)
sub SVE Integer Subtract (Predicated)

Reference

View in Arm A64 ISA Reference ↗ Arm AArch32 ISA

Instruction Forms

Encoding	Instruction	ISA	Bit pattern
0x024F0000	SUB{<c>}{<q>} <Rd>, PC, #<const>	A32	cond \| 0010 \| 010 \| 0 \| 1111 \| Rd \| imm12
0xF2AF0000	SUB{<c>}{<q>} <Rd>, PC, #<imm12>	T32	11110 \| i \| 10 \| 1 \| 0 \| 1 \| 0 \| 1111 \| 0 \| imm3 \| Rd \| imm8
0x02400000	SUB{<c>}{<q>} {<Rd>,} <Rn>, #<const>	A32	cond \| 0010 \| 010 \| 0 \| Rn \| Rd \| imm12
0x1E00	SUB<c>{<q>} <Rd>, <Rn>, #<imm3>	T32	000111 \| 1 \| imm3 \| Rn \| Rd
0x3800	SUB<c>{<q>} <Rdn>, #<imm8>	T32	001 \| 11 \| Rdn \| imm8
0xF1A00000	SUB<c>.W {<Rd>,} <Rn>, #<const>	T32	11110 \| i \| 0 \| 1101 \| 0 \| Rn \| 0 \| imm3 \| Rd \| imm8
0x00400060	SUB{<c>}{<q>} {<Rd>,} <Rn>, <Rm>, RRX	A32	cond \| 0000 \| 010 \| 0 \| Rn \| Rd \| 00000 \| 11 \| 0 \| Rm
0x00400000	SUB{<c>}{<q>} {<Rd>,} <Rn>, <Rm> {, <shift> #<amount>}	A32	cond \| 0000 \| 010 \| 0 \| Rn \| Rd \| imm5 \| stype \| 0 \| Rm
0x1A00	SUB<c>{<q>} <Rd>, <Rn>, <Rm>	T32	000110 \| 1 \| Rm \| Rn \| Rd
0xEBA00030	SUB{<c>}{<q>} {<Rd>,} <Rn>, <Rm>, RRX	T32	1110101 \| 1101 \| 0 \| Rn \| 0 \| 000 \| Rd \| 00 \| 11 \| Rm
0xEBA00000	SUB<c>.W {<Rd>,} <Rn>, <Rm>	T32	1110101 \| 1101 \| 0 \| Rn \| 0 \| imm3 \| Rd \| imm2 \| stype \| Rm
0x00400010	SUB{<c>}{<q>} {<Rd>,} <Rn>, <Rm>, <shift> <Rs>	A32	cond \| 0000 \| 010 \| 0 \| Rn \| Rd \| Rs \| 0 \| stype \| 1 \| Rm
0x024D0000	SUB{<c>}{<q>} {<Rd>,} SP, #<const>	A32	cond \| 0010 \| 010 \| 0 \| 1101 \| Rd \| imm12
0xB080	SUB{<c>}{<q>} {SP,} SP, #<imm7>	T32	10110000 \| 1 \| imm7

Description

Subtract (immediate) subtracts an immediate value from a register value, and writes the result to the destination register. If the destination register is not the PC, the SUBS variant of the instruction updates the condition flags based on the result. The field descriptions for <Rd> identify the encodings where the PC is permitted as the destination register. If the destination register is the PC:

Operation

if ConditionPassed() then
    EncodingSpecificOperations();
    (result, nzcv) = AddWithCarry(R[n], NOT(imm32), '1');
    if d == 15 then
        if setflags then
            ALUExceptionReturn(result);
        else
            ALUWritePC(result);
    else
        R[d] = result;
        if setflags then
            PSTATE.<N,Z,C,V> = nzcv;

sub