smusd

Signed Multiply Subtract Dual

SMUSD{X}<c> <Rd>, <Rn>, <Rm>

Performs two 16x16 multiplies and subtracts results.

Pseudocode Operation

if X then
  prod1 ← SignExtend(Rn[31:16], 32) × SignExtend(Rm[15:0], 32)
  prod2 ← SignExtend(Rn[15:0], 32) × SignExtend(Rm[31:16], 32)
else
  prod1 ← SignExtend(Rn[31:16], 32) × SignExtend(Rm[31:16], 32)
  prod2 ← SignExtend(Rn[15:0], 32) × SignExtend(Rm[15:0], 32)
Rd ← prod1 - prod2

Example

SMUSD r0, r1, r2

Encoding

Binary Layout

cond

31:28

01110

27:23

000

22:20

Rd

19:16

1111

15:12

Rm

11:8

01

7:6

0

5

1

4

Rn

3:0

 

Format Multiply

Opcode 0x0700F050

Extension A32 (DSP)

Operands

• Rd
  Destination general-purpose register
• Rn
  First source / base general-purpose register
• Rm
  Second source / offset general-purpose register

Related

More in A32 (DSP)

Reference

View in Arm A64 ISA Reference ↗ Arm AArch32 ISA

Instruction Forms

Encoding	Instruction		ISA		Bit pattern
0x0700F050	SMUSD{<c>}{<q>} {<Rd>,} <Rn>, <Rm>		A32		cond | 01110 | 000 | Rd | 1111 | Rm | 01 | 0 | 1 | Rn
0xFB40F000	SMUSD{<c>}{<q>} {<Rd>,} <Rn>, <Rm>		T32		111110110 | 100 | Rn | 1111 | Rd | 00 | 0 | 0 | Rm

Description

Signed Multiply Subtract Dual performs two signed 16 x 16-bit multiplications. It subtracts one of the products from the other, and writes the result to the destination register. Optionally, the instruction can exchange the halfwords of the second operand before performing the arithmetic. This produces top x bottom and bottom x top multiplication. Overflow cannot occur.

Operation

if ConditionPassed() then
    EncodingSpecificOperations();
    operand2 = if m_swap then ROR(R[m],16) else R[m];
    product1 = SInt(R[n]<15:0>) * SInt(operand2<15:0>);
    product2 = SInt(R[n]<31:16>) * SInt(operand2<31:16>);
    result = product1 - product2;
    R[d] = result<31:0>;
    // Signed overflow cannot occur