smusd

Signed Multiply Subtract Dual

SMUSD{X}<c> <Rd>, <Rn>, <Rm>

Performs two 16x16 multiplies and subtracts results.

Details

Multiplies two pairs of signed 16-bit values and subtracts: (Rn[31:16] × Rm[31:16]) − (Rn[15:0] × Rm[15:0]), storing the 32-bit signed result in Rd. The {X} variant swaps the operands of one multiply. The instruction does not update condition flags. A32 DSP extension only.

Pseudocode Operation

if X then
  prod1 ← SignExtend(Rn[31:16], 32) × SignExtend(Rm[15:0], 32)
  prod2 ← SignExtend(Rn[15:0], 32) × SignExtend(Rm[31:16], 32)
else
  prod1 ← SignExtend(Rn[31:16], 32) × SignExtend(Rm[31:16], 32)
  prod2 ← SignExtend(Rn[15:0], 32) × SignExtend(Rm[15:0], 32)
Rd ← prod1 - prod2

Example

SMUSD r0, r1, r2

Encoding

Binary Layout
cond
01110
000
Rd
1111
Rm
01
0
1
Rn
 
Format Multiply
Opcode 0x0700F050
Extension A32 (DSP)

Operands

  • Rd
    Destination general-purpose register
  • Rn
    First source / base general-purpose register
  • Rm
    Second source / offset general-purpose register

Reference (Arm AArch32 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0x0700F050 SMUSD{<c>}{<q>} {<Rd>,} <Rn>, <Rm> A32 cond | 01110 | 000 | Rd | 1111 | Rm | 01 | 0 | 1 | Rn
0xFB40F000 SMUSD{<c>}{<q>} {<Rd>,} <Rn>, <Rm> T32 111110110 | 100 | Rn | 1111 | Rd | 00 | 0 | 0 | Rm

Description

Signed Multiply Subtract Dual performs two signed 16 x 16-bit multiplications. It subtracts one of the products from the other, and writes the result to the destination register. Optionally, the instruction can exchange the halfwords of the second operand before performing the arithmetic. This produces top x bottom and bottom x top multiplication. Overflow cannot occur.

Operation

if ConditionPassed() then
    EncodingSpecificOperations();
    operand2 = if m_swap then ROR(R[m],16) else R[m];
    product1 = SInt(R[n]<15:0>) * SInt(operand2<15:0>);
    product2 = SInt(R[n]<31:16>) * SInt(operand2<31:16>);
    result = product1 - product2;
    R[d] = result<31:0>;
    // Signed overflow cannot occur