ld1b

SVE Load Contiguous Bytes

LD1B { <Zt>.B }, <Pg>/Z, [<Xn|SP>]

Loads bytes from memory into a vector under predicate control.

Pseudocode Operation

for i = 0 to VL/8-1
  if Pg[i] == 1 then
    Zt.B[i] ← [Xn + i]
  else
    Zt.B[i] ← 0

Example

LD1B p0/m/Z, [x1]

Encoding

Binary Layout

1010010

31:25

000

24:22

0

21

Rm

20:16

010

15:13

Pg

12:10

Rn

9:5

Zt

4:0

 

Format SVE Load

Opcode 0xA4004000

Extension SVE

Operands

• Zt
  Dest Vector
• Pg
  Predicate
• Xn
  Base Addr

Related

More in SVE

Reference

View in Arm A64 ISA Reference ↗ Arm A64 ISA

Instruction Forms

Encoding	Instruction		ISA		Bit pattern
0xA0400000	LD1B { <Zt1>.B-<Zt2>.B }, <PNg>/Z, [<Xn|SP>{, #<imm>, MUL VL}]		A64		101000000100 | imm4 | 0 | 0 | 0 | PNg | Rn | Zt | 0
0xA0408000	LD1B { <Zt1>.B-<Zt4>.B }, <PNg>/Z, [<Xn|SP>{, #<imm>, MUL VL}]		A64		101000000100 | imm4 | 1 | 0 | 0 | PNg | Rn | Zt | 0 | 0
0xA0000000	LD1B { <Zt1>.B-<Zt2>.B }, <PNg>/Z, [<Xn|SP>, <Xm>]		A64		10100000000 | Rm | 0 | 0 | 0 | PNg | Rn | Zt | 0
0xA0008000	LD1B { <Zt1>.B-<Zt4>.B }, <PNg>/Z, [<Xn|SP>, <Xm>]		A64		10100000000 | Rm | 1 | 0 | 0 | PNg | Rn | Zt | 0 | 0
0xA1400000	LD1B { <Zt1>.B, <Zt2>.B }, <PNg>/Z, [<Xn|SP>{, #<imm>, MUL VL}]		A64		101000010100 | imm4 | 0 | 0 | 0 | PNg | Rn | T | 0 | Zt
0xA1408000	LD1B { <Zt1>.B, <Zt2>.B, <Zt3>.B, <Zt4>.B }, <PNg>/Z, [<Xn|SP>{, #<imm>, MUL VL}]		A64		101000010100 | imm4 | 1 | 0 | 0 | PNg | Rn | T | 0 | 0 | Zt
0xA1000000	LD1B { <Zt1>.B, <Zt2>.B }, <PNg>/Z, [<Xn|SP>, <Xm>]		A64		10100001000 | Rm | 0 | 0 | 0 | PNg | Rn | T | 0 | Zt
0xA1008000	LD1B { <Zt1>.B, <Zt2>.B, <Zt3>.B, <Zt4>.B }, <PNg>/Z, [<Xn|SP>, <Xm>]		A64		10100001000 | Rm | 1 | 0 | 0 | PNg | Rn | T | 0 | 0 | Zt
0x8420C000	LD1B { <Zt>.S }, <Pg>/Z, [<Zn>.S{, #<imm>}]		A64		1000010 | 0 | 0 | 01 | imm5 | 1 | 1 | 0 | Pg | Zn | Zt
0xC420C000	LD1B { <Zt>.D }, <Pg>/Z, [<Zn>.D{, #<imm>}]		A64		1100010 | 0 | 0 | 01 | imm5 | 1 | 1 | 0 | Pg | Zn | Zt
0xA400A000	LD1B { <Zt>.B }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}]		A64		1010010 | 000 | 0 | 0 | imm4 | 101 | Pg | Rn | Zt
0xA420A000	LD1B { <Zt>.H }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}]		A64		1010010 | 000 | 1 | 0 | imm4 | 101 | Pg | Rn | Zt
0xA440A000	LD1B { <Zt>.S }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}]		A64		1010010 | 001 | 0 | 0 | imm4 | 101 | Pg | Rn | Zt
0xA460A000	LD1B { <Zt>.D }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}]		A64		1010010 | 001 | 1 | 0 | imm4 | 101 | Pg | Rn | Zt

Description

Contiguous load of unsigned bytes to elements of a vector register from the memory address generated by a 64-bit scalar base and scalar index which is added to the base address. After each element access the index value is incremented, but the index register is not updated. Inactive elements will not cause a read from Device memory or signal a fault, and are set to zero in the destination vector.

Operation

CheckSVEEnabled();
constant integer VL = CurrentVL;
constant integer PL = VL DIV 8;
constant integer elements = VL DIV esize;
bits(64) base;
bits(PL) mask = P[g, PL];
bits(VL) result;
bits(msize) data;
bits(64) offset;
constant integer mbytes = msize DIV 8;
boolean contiguous = TRUE;
boolean nontemporal = FALSE;
boolean tagchecked = TRUE;
AccessDescriptor accdesc = CreateAccDescSVE(MemOp_LOAD, nontemporal, contiguous, tagchecked);

if !AnyActiveElement(mask, esize) then
    if n == 31 && ConstrainUnpredictableBool(Unpredictable_CHECKSPNONEACTIVE) then
        CheckSPAlignment();
else
    if n == 31 then CheckSPAlignment();
    base = if n == 31 then SP[] else X[n, 64];
    offset = X[m, 64];

for e = 0 to elements-1
    if ActivePredicateElement(mask, e, esize) then
        integer eoff = UInt(offset) + e;
        bits(64) addr = GenerateAddress(base, eoff * mbytes, accdesc);
        data = Mem[addr, mbytes, accdesc];
        Elem[result, e, esize] = Extend(data, esize, unsigned);
    else
        Elem[result, e, esize] = Zeros(esize);

Z[t, VL] = result;