shrn

Shift Right Narrow

SHRN <Vd>.<Tb>, <Vn>.<Ta>, #<shift>

Shifts wide vector right, narrowing to destination (Upper/Lower).

Pseudocode Operation

for i = 0 to elements-1 do
  temp ← Vn[i] >> shift
  Vd[i] ← temp[element_width_dest-1:0]
endfor

Example

SHRN v0.4s.Tb, v1.4s.Ta, #LSL

Encoding

Binary Layout

011110

28:23

immh

22:19

immb

18:16

1000

15:12

9:5

4:0

Format SIMD Shift Imm

Opcode 0x0F008400

Extension NEON (SIMD)

Operands

Vd
Dest (Narrow)
Vn
Src (Wide)
shift
Imm

Reference

View in Arm A64 ISA Reference ↗ Arm A64 ISA

Instruction Forms

Encoding	Instruction		ISA		Bit pattern
0x0F008400	SHRN{2} <Vd>.<Tb>, <Vn>.<Ta>, #<shift>		A64		0 \| Q \| 0 \| 011110 \| immh \| immb \| 1000 \| 0 \| 1 \| Rn \| Rd

Description

Shift Right Narrow (immediate). This instruction reads each unsigned integer value from the source SIMD&FP register, right shifts each result by an immediate value, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are half as long as the source vector elements. The results are truncated. For rounded results, see RSHRN. The RSHRN instruction writes the vector to the lower half of the destination register and clears the upper half, while the RSHRN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register. Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize*2) operand = V[n, datasize*2];
bits(datasize) result;
integer element;

for e = 0 to elements-1
    element = RShr(UInt(Elem[operand, e, 2*esize]), shift, round);
    Elem[result, e, esize] = element<esize-1:0>;

Vpart[d, part, datasize] = result;