fcmgt

SVE Floating-Point Compare Greater Than

FCMGT <Pd>.<T>, <Pg>/Z, <Zn>.<T>, <Zm>.<T>

Sets predicate bits where float Zn > Zm.

Pseudocode Operation

for i = 0 to VL/esize-1
  if Pg[i] == 1
    Pd[i] ← (Zn[i, esize] > Zm[i, esize]) ? 1 : 0
  else
    Pd[i] ← 0

Example

FCMGT p0.s, p1/z, z1.s, z2.s

Encoding

Binary Layout

01100101

31:24

size

23:22

0

21

Zm

20:16

0

15

1

14

0

13

Pg

12:10

Zn

9:5

1

4

Pd

3:0

 

Format SVE FP Compare

Opcode 0x65004010

Extension SVE

Operands

• Pd
  Dest Pred
• Pg
  Mask
• Zn
  First source scalable vector register (SVE)
• Zm
  Second source scalable vector register (SVE)

Related

More in SVE

Reference

View in Arm A64 ISA Reference ↗ Arm A64 ISA

Instruction Forms

Encoding	Instruction		ISA		Bit pattern
0x65102010	FCMGT <Pd>.<T>, <Pg>/Z, <Zn>.<T>, #0.0		A64		01100101 | size | 0100 | 0 | 0 | 001 | Pg | Zn | 1 | Pd
0x65004010	FCMGT <Pd>.<T>, <Pg>/Z, <Zn>.<T>, <Zm>.<T>		A64		01100101 | size | 0 | Zm | 0 | 1 | 0 | Pg | Zn | 1 | Pd
0x7EC02400	FCMGT <Hd>, <Hn>, <Hm>		A64		01 | 1 | 11110 | 1 | 10 | Rm | 0010 | 0 | 1 | Rn | Rd
0x7EA0E400	FCMGT <V><d>, <V><n>, <V><m>		A64		01 | 1 | 11110 | 1 | sz | 1 | Rm | 1110 | 0 | 1 | Rn | Rd
0x2EC02400	FCMGT <Vd>.<T>, <Vn>.<T>, <Vm>.<T>		A64		0 | Q | 1 | 01110 | 1 | 10 | Rm | 0010 | 0 | 1 | Rn | Rd
0x2EA0E400	FCMGT <Vd>.<T>, <Vn>.<T>, <Vm>.<T>		A64		0 | Q | 1 | 01110 | 1 | sz | 1 | Rm | 1110 | 0 | 1 | Rn | Rd
0x5EF8C800	FCMGT <Hd>, <Hn>, #0.0		A64		01 | 0 | 11110 | 1 | 1111000110 | 0 | 10 | Rn | Rd
0x5EA0C800	FCMGT <V><d>, <V><n>, #0.0		A64		01 | 0 | 111101 | sz | 100000110 | 0 | 10 | Rn | Rd
0x0EF8C800	FCMGT <Vd>.<T>, <Vn>.<T>, #0.0		A64		0 | Q | 0 | 01110 | 1 | 1111000110 | 0 | 10 | Rn | Rd
0x0EA0C800	FCMGT <Vd>.<T>, <Vn>.<T>, #0.0		A64		0 | Q | 0 | 011101 | sz | 100000110 | 0 | 10 | Rn | Rd

Description

Compare active floating-point elements in the first source vector with corresponding elements in the second source vector, and place the boolean results of the specified comparison in the corresponding elements of the destination predicate. Inactive elements in the destination predicate register are set to zero. Does not set the condition flags.

Operation

CheckSVEEnabled();
constant integer VL = CurrentVL;
constant integer PL = VL DIV 8;
constant integer elements = VL DIV esize;
bits(PL) mask = P[g, PL];
bits(VL) operand1 = if AnyActiveElement(mask, esize) then Z[n, VL] else Zeros(VL);
bits(VL) operand2 = if AnyActiveElement(mask, esize) then Z[m, VL] else Zeros(VL);
bits(PL) result;
constant integer psize = esize DIV 8;

for e = 0 to elements-1
    if ActivePredicateElement(mask, e, esize) then
        bits(esize) element1 = Elem[operand1, e, esize];
        bits(esize) element2 = Elem[operand2, e, esize];
        boolean res;
        case op of
            when Cmp_EQ res = FPCompareEQ(element1, element2, FPCR);
            when Cmp_GE res = FPCompareGE(element1, element2, FPCR);
            when Cmp_GT res = FPCompareGT(element1, element2, FPCR);
            when Cmp_UN res = FPCompareUN(element1, element2, FPCR);
            when Cmp_NE res = FPCompareNE(element1, element2, FPCR);
            when Cmp_LT res = FPCompareGT(element2, element1, FPCR);
            when Cmp_LE res = FPCompareGE(element2, element1, FPCR);
        bit pbit = if res then '1' else '0';
        Elem[result, e, psize] = ZeroExtend(pbit, psize);
    else
        Elem[result, e, psize] = ZeroExtend('0', psize);

P[d, PL] = result;