ldr.w

Load Register (Wide)

LDR.W <Rt>, [<Rn>, #<imm>]

Thumb-2 32-bit Load Word.

Details

Load a 32-bit word from memory at address [Rn + imm12] into Rt. The immediate offset is unsigned and ranges from 0 to 4095 bytes. Condition flags (N, Z, C, V) are not affected. T32 (Thumb-2) instruction only.

Pseudocode Operation

address ← Rn + ZeroExtend(imm12, 32);
Rt ← [address]<31:0>;

Example

LDR.W r3, [r1, #16]

Encoding

Binary Layout
111110001
10
1
Rn
Rt
imm12
 
Format Thumb Load
Opcode 0xF8D00000
Extension T32 (Thumb2)

Operands

  • Rt
    Transfer general-purpose register (load/store)
  • Rn
    First source / base general-purpose register
  • imm
    Signed immediate value

Reference (Arm AArch32 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0x05100000 LDR{<c>}{<q>} <Rt>, [<Rn> {, #{+/-}<imm>}] A32 cond | 010 | 1 | U | 0 | 0 | 1 | Rn | Rt | imm12
0x04100000 LDR{<c>}{<q>} <Rt>, [<Rn>], #{+/-}<imm> A32 cond | 010 | 0 | U | 0 | 0 | 1 | Rn | Rt | imm12
0x05300000 LDR{<c>}{<q>} <Rt>, [<Rn>, #{+/-}<imm>]! A32 cond | 010 | 1 | U | 0 | 1 | 1 | Rn | Rt | imm12
0x6800 LDR{<c>}{<q>} <Rt>, [<Rn> {, #{+}<imm>}] T32 011 | 0 | 1 | imm5 | Rn | Rt
0x9800 LDR{<c>}{<q>} <Rt>, [SP{, #{+}<imm>}] T32 1001 | 1 | Rt | imm8
0xF8D00000 LDR{<c>}.W <Rt>, [<Rn> {, #{+}<imm>}] T32 111110001 | 10 | 1 | Rn | Rt | imm12
0xF8500C00 LDR{<c>}{<q>} <Rt>, [<Rn> {, #-<imm>}] T32 111110000 | 10 | 1 | Rn | Rt | 1 | 1 | 0 | 0 | imm8
0xF8500900 LDR{<c>}{<q>} <Rt>, [<Rn>], #{+/-}<imm> T32 111110000 | 10 | 1 | Rn | Rt | 1 | 0 | U | 1 | imm8
0xF8500D00 LDR{<c>}{<q>} <Rt>, [<Rn>, #{+/-}<imm>]! T32 111110000 | 10 | 1 | Rn | Rt | 1 | 1 | U | 1 | imm8
0x041F0000 LDR{<c>}{<q>} <Rt>, <label> A32 cond | 010 | P | U | 0 | W | 1 | 1111 | Rt | imm12
0x4800 LDR{<c>}{<q>} <Rt>, <label> T32 01001 | Rt | imm8
0xF85F0000 LDR{<c>}.W <Rt>, <label> T32 11111000 | U | 10 | 1 | 1111 | Rt | imm12
0x07100000 LDR{<c>}{<q>} <Rt>, [<Rn>, {+/-}<Rm>{, <shift>}] A32 cond | 011 | 1 | U | 0 | 0 | 1 | Rn | Rt | imm5 | stype | 0 | Rm
0x06100000 LDR{<c>}{<q>} <Rt>, [<Rn>], {+/-}<Rm>{, <shift>} A32 cond | 011 | 0 | U | 0 | 0 | 1 | Rn | Rt | imm5 | stype | 0 | Rm

Description

Load Register (immediate) calculates an address from a base register value and an immediate offset, loads a word from memory, and writes it to a register. It can use offset, post-indexed, or pre-indexed addressing. For information about memory accesses see Memory accesses.

Operation

if CurrentInstrSet() == InstrSet_A32 then
    if ConditionPassed() then
        EncodingSpecificOperations();
        offset_addr = if add then (R[n] + imm32) else (R[n] - imm32);
        address = if index then offset_addr else R[n];
        data = MemU[address,4];
        if wback then R[n] = offset_addr;
        if t == 15 then
            if address<1:0> == '00' then
                LoadWritePC(data);
            else
                UNPREDICTABLE;
        else
            R[t] = data;
else
    if ConditionPassed() then
        EncodingSpecificOperations();
        offset_addr = if add then (R[n] + imm32) else (R[n] - imm32);
        address = if index then offset_addr else R[n];
        data = MemU[address,4];
        if wback then R[n] = offset_addr;
        if t == 15 then
            if address<1:0> == '00' then
                LoadWritePC(data);
            else
                UNPREDICTABLE;
        else
            R[t] = data;