vcvtb

Vector Convert Half-Precision (Bottom)

VCVTB<c>.F16.F32 <Sd>, <Sm>

Converts single-precision to half-precision (Bottom half).

Details

Converts a single-precision floating-point value to half-precision and stores it in the bottom half of the destination single-precision register. The top half of the destination is unchanged. The instruction is conditional and sets VFP flags (FPSCR) according to the conversion result.

Pseudocode Operation

Sd[15:0] ← ConvertToHalf(Sm); Sd[31:16] unchanged

Example

VCVTB.F16.F32 s0, s2

Encoding

Binary Layout
cond
11101
D
11
0
01
0
Vd
10
1
0
0
1
M
0
Vm
 
Format VFP Convert
Opcode 0x0EB20A40
Extension VFP (Half)

Operands

  • Sd
    Dest (Half)
  • Sm
    Src (Single)

Reference (Arm AArch32 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0x0EB20A40 VCVTB{<c>}{<q>}.F32.F16 <Sd>, <Sm> A32 cond | 11101 | D | 11 | 0 | 01 | 0 | Vd | 10 | 1 | 0 | 0 | 1 | M | 0 | Vm
0x0EB20B40 VCVTB{<c>}{<q>}.F64.F16 <Dd>, <Sm> A32 cond | 11101 | D | 11 | 0 | 01 | 0 | Vd | 10 | 1 | 1 | 0 | 1 | M | 0 | Vm
0x0EB30A40 VCVTB{<c>}{<q>}.F16.F32 <Sd>, <Sm> A32 cond | 11101 | D | 11 | 0 | 01 | 1 | Vd | 10 | 1 | 0 | 0 | 1 | M | 0 | Vm
0x0EB30B40 VCVTB{<c>}{<q>}.F16.F64 <Sd>, <Dm> A32 cond | 11101 | D | 11 | 0 | 01 | 1 | Vd | 10 | 1 | 1 | 0 | 1 | M | 0 | Vm
0xEEB20A40 VCVTB{<c>}{<q>}.F32.F16 <Sd>, <Sm> T32 111011101 | D | 11 | 0 | 01 | 0 | Vd | 10 | 1 | 0 | 0 | 1 | M | 0 | Vm
0xEEB20B40 VCVTB{<c>}{<q>}.F64.F16 <Dd>, <Sm> T32 111011101 | D | 11 | 0 | 01 | 0 | Vd | 10 | 1 | 1 | 0 | 1 | M | 0 | Vm
0xEEB30A40 VCVTB{<c>}{<q>}.F16.F32 <Sd>, <Sm> T32 111011101 | D | 11 | 0 | 01 | 1 | Vd | 10 | 1 | 0 | 0 | 1 | M | 0 | Vm
0xEEB30B40 VCVTB{<c>}{<q>}.F16.F64 <Sd>, <Dm> T32 111011101 | D | 11 | 0 | 01 | 1 | Vd | 10 | 1 | 1 | 0 | 1 | M | 0 | Vm
0x0EB30940 VCVTB{<c>}{<q>}.BF16.F32 <Sd>, <Sm> A32 cond | 11101 | D | 11 | 0 | 011 | Vd | 10 | 01 | 0 | 1 | M | 0 | Vm
0xEEB30940 VCVTB{<c>}{<q>}.BF16.F32 <Sd>, <Sm> T32 111011101 | D | 11 | 0 | 011 | Vd | 10 | 01 | 0 | 1 | M | 0 | Vm

Description

Convert to or from a half-precision value in the bottom half of a single-precision register does one of the following: Depending on settings in the CPACR, NSACR, HCPTR, and FPEXC registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be undefined, or trapped to Hyp mode. For more information see Enabling Advanced SIMD and floating-point support.

Operation

if ConditionPassed() then
    EncodingSpecificOperations(); CheckVFPEnabled(TRUE);
    bits(16) hp;
    if convert_from_half then
        hp = S[m]<lowbit+15:lowbit>;
        if uses_double then
            D[d] = FPConvert(hp, FPSCR[], 64);
        else
            S[d] = FPConvert(hp, FPSCR[], 32);
    else
        if uses_double then
            hp = FPConvert(D[m], FPSCR[], 16);
        else
            hp = FPConvert(S[m], FPSCR[], 16);
        S[d]<lowbit+15:lowbit> = hp;