vld2

Vector Load Multiple (2-Element Structure)

VLD2<c>.<size> <list>, [<Rn>]{!}

De-interleaves 2 streams of data while loading.

Pseudocode Operation

address ← Rn
for each 2-element structure at address
  element0 ← memory[address]
  element1 ← memory[address + size_bytes]
  store element0 in first destination register
  store element1 in second destination register
  address ← address + 2 * size_bytes
if writeback
  Rn ← Rn + total_bytes_loaded

Example

VLD2.size {r0-r3}, [r1]!

Encoding

Binary Layout
111101001
31:23
D
22
1
21
0
20
Rn
19:16
Vd
15:12
00
11:10
01
9:8
index_align
7:4
1101
3:0
 
Format NEON Load
Opcode 0xF4A0010D
Extension NEON (SIMD)

Operands

  • list
    Dest Registers
  • Rn
    First source / base general-purpose register

Related

More in NEON (SIMD)

Reference

View in Arm A64 ISA Reference ↗ Arm AArch32 ISA

Instruction Forms

Encoding Instruction ISA Bit pattern
0xF4A0010F VLD2{<c>}{<q>}.<size> <list>, [<Rn>{:<align>}] A32 111101001 | D | 1 | 0 | Rn | Vd | 00 | 01 | index_align | 1111
0xF4A0010D VLD2{<c>}{<q>}.<size> <list>, [<Rn>{:<align>}]! A32 111101001 | D | 1 | 0 | Rn | Vd | 00 | 01 | index_align | 1101
0xF4A00100 VLD2{<c>}{<q>}.<size> <list>, [<Rn>{:<align>}], <Rm> A32 111101001 | D | 1 | 0 | Rn | Vd | 00 | 01 | index_align | Rm
0xF4A0050F VLD2{<c>}{<q>}.<size> <list>, [<Rn>{:<align>}] A32 111101001 | D | 1 | 0 | Rn | Vd | 01 | 01 | index_align | 1111
0xF4A0050D VLD2{<c>}{<q>}.<size> <list>, [<Rn>{:<align>}]! A32 111101001 | D | 1 | 0 | Rn | Vd | 01 | 01 | index_align | 1101
0xF4A00500 VLD2{<c>}{<q>}.<size> <list>, [<Rn>{:<align>}], <Rm> A32 111101001 | D | 1 | 0 | Rn | Vd | 01 | 01 | index_align | Rm
0xF4A0090F VLD2{<c>}{<q>}.<size> <list>, [<Rn>{:<align>}] A32 111101001 | D | 1 | 0 | Rn | Vd | 10 | 01 | index_align | 1111
0xF4A0090D VLD2{<c>}{<q>}.<size> <list>, [<Rn>{:<align>}]! A32 111101001 | D | 1 | 0 | Rn | Vd | 10 | 01 | index_align | 1101
0xF4A00900 VLD2{<c>}{<q>}.<size> <list>, [<Rn>{:<align>}], <Rm> A32 111101001 | D | 1 | 0 | Rn | Vd | 10 | 01 | index_align | Rm
0xF9A0010F VLD2{<c>}{<q>}.<size> <list>, [<Rn>{:<align>}] T32 111110011 | D | 1 | 0 | Rn | Vd | 00 | 01 | index_align | 1111
0xF9A0010D VLD2{<c>}{<q>}.<size> <list>, [<Rn>{:<align>}]! T32 111110011 | D | 1 | 0 | Rn | Vd | 00 | 01 | index_align | 1101
0xF9A00100 VLD2{<c>}{<q>}.<size> <list>, [<Rn>{:<align>}], <Rm> T32 111110011 | D | 1 | 0 | Rn | Vd | 00 | 01 | index_align | Rm
0xF9A0050F VLD2{<c>}{<q>}.<size> <list>, [<Rn>{:<align>}] T32 111110011 | D | 1 | 0 | Rn | Vd | 01 | 01 | index_align | 1111
0xF9A0050D VLD2{<c>}{<q>}.<size> <list>, [<Rn>{:<align>}]! T32 111110011 | D | 1 | 0 | Rn | Vd | 01 | 01 | index_align | 1101

Description

Load single 2-element structure to one lane of two registers loads one 2-element structure from memory into corresponding elements of two registers. Elements of the registers that are not loaded are unchanged. For details of the addressing mode, see Advanced SIMD addressing mode. Depending on settings in the CPACR, NSACR, and HCPTR registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be undefined, or trapped to Hyp mode. For more information, see Enabling Advanced SIMD and floating-point support.

Operation

if ConditionPassed() then
    EncodingSpecificOperations();
    CheckAdvSIMDEnabled();

    address = R[n];

    boolean nontemporal = FALSE;
    boolean tagchecked  = FALSE;
    AccessDescriptor accdesc = CreateAccDescASIMD(MemOp_LOAD, nontemporal, tagchecked);
    if !IsAligned(address, alignment) then
        AArch32.Abort(address, AlignmentFault(accdesc));

    Elem[D[d], index,8*ebytes] = MemU[address,ebytes];
    Elem[D[d2],index,8*ebytes] = MemU[address+ebytes,ebytes];
    if wback then
        if register_index then
            R[n] = R[n] + R[m];
        else
            R[n] = R[n] + 2*ebytes;