clz

Vector Count Leading Zeros

CLZ <Vd>.<T>, <Vn>.<T>

Counts leading zeros for each element.

Pseudocode Operation

for i = 0 to elements-1 do
  Vd[i] ← CountLeadingZeros(Vn[i])
endfor

Example

CLZ v0.4s.T, v1.4s.T

Encoding

Binary Layout

01110

28:24

size

23:22

10000

21:17

00100

16:12

11:10

9:5

4:0

Format SIMD Two Register

Opcode 0x2E204800

Extension NEON (SIMD)

Operands

Vd
Destination SIMD/FP vector register
Vn
First source SIMD/FP vector register

Other forms of clz

clz Count Leading Zeros
clz Count Leading Zeros (Thumb)
clz Count Leading Zeros (A32)

Across architectures

Count Leading Zeros : how x86, ARM, RISC-V, and PowerISA each do this.

Reference

View in Arm A64 ISA Reference ↗ Arm A64 ISA

Instruction Forms

Encoding	Instruction	ISA	Bit pattern
0x2E204800	CLZ <Vd>.<T>, <Vn>.<T>	A64	0 \| Q \| 1 \| 01110 \| size \| 10000 \| 00100 \| 10 \| Rn \| Rd
0x5AC01000	CLZ <Wd>, <Wn>	A64	0 \| 1 \| 0 \| 11010110 \| 00000 \| 00010 \| 0 \| Rn \| Rd
0xDAC01000	CLZ <Xd>, <Xn>	A64	1 \| 1 \| 0 \| 11010110 \| 00000 \| 00010 \| 0 \| Rn \| Rd
0x0419A000	CLZ <Zd>.<T>, <Pg>/M, <Zn>.<T>	A64	00000100 \| size \| 011 \| 00 \| 1 \| 101 \| Pg \| Zn \| Zd

Description

Count Leading Zero bits (vector). This instruction counts the number of consecutive zeros, starting from the most significant bit, in each vector element in the source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register. Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand = V[n, datasize];
bits(datasize) result;

integer count;
for e = 0 to elements-1
    if countop == CountOp_CLS then
        count = CountLeadingSignBits(Elem[operand, e, esize]);
    else
        count = CountLeadingZeroBits(Elem[operand, e, esize]);
    Elem[result, e, esize] = count<esize-1:0>;
V[d, datasize] = result;

clz