vst3

Vector Store Multiple (3-Element Structure)

VST3<c>.<size> <list>, [<Rn>]{!}

Interleaves and stores three registers into memory (e.g., RGB).

Pseudocode Operation

address ← Rn
for i = 0 to 7 do
  element_size_bits ← size_in_bits(size)
  [address + (i * element_size_bits / 8)] ← Vd[i]
  [address + (i * element_size_bits / 8) + (element_size_bits / 8)] ← Vd+1[i]
  [address + (i * element_size_bits / 8) + (2 * element_size_bits / 8)] ← Vd+2[i]
if (writeback) then
  Rn ← Rn + (3 * 8 * element_size_bits / 8)

Example

VST3.size {r0-r3}, [r1]!

Encoding

Binary Layout
111101001
31:23
D
22
0
21
0
20
Rn
19:16
Vd
15:12
00
11:10
10
9:8
index_align
7:4
1101
3:0
 
Format NEON Store
Opcode 0xF480020D
Extension NEON (SIMD)

Operands

  • list
    Src Registers
  • Rn
    First source / base general-purpose register

Related

More in NEON (SIMD)

Reference

View in Arm A64 ISA Reference ↗ Arm AArch32 ISA

Instruction Forms

Encoding Instruction ISA Bit pattern
0xF480020F VST3{<c>}{<q>}.<size> <list>, [<Rn>] A32 111101001 | D | 0 | 0 | Rn | Vd | 00 | 10 | index_align | 1111
0xF480020D VST3{<c>}{<q>}.<size> <list>, [<Rn>]! A32 111101001 | D | 0 | 0 | Rn | Vd | 00 | 10 | index_align | 1101
0xF4800200 VST3{<c>}{<q>}.<size> <list>, [<Rn>], <Rm> A32 111101001 | D | 0 | 0 | Rn | Vd | 00 | 10 | index_align | Rm
0xF480060F VST3{<c>}{<q>}.<size> <list>, [<Rn>] A32 111101001 | D | 0 | 0 | Rn | Vd | 01 | 10 | index_align | 1111
0xF480060D VST3{<c>}{<q>}.<size> <list>, [<Rn>]! A32 111101001 | D | 0 | 0 | Rn | Vd | 01 | 10 | index_align | 1101
0xF4800600 VST3{<c>}{<q>}.<size> <list>, [<Rn>], <Rm> A32 111101001 | D | 0 | 0 | Rn | Vd | 01 | 10 | index_align | Rm
0xF4800A0F VST3{<c>}{<q>}.<size> <list>, [<Rn>] A32 111101001 | D | 0 | 0 | Rn | Vd | 10 | 10 | index_align | 1111
0xF4800A0D VST3{<c>}{<q>}.<size> <list>, [<Rn>]! A32 111101001 | D | 0 | 0 | Rn | Vd | 10 | 10 | index_align | 1101
0xF4800A00 VST3{<c>}{<q>}.<size> <list>, [<Rn>], <Rm> A32 111101001 | D | 0 | 0 | Rn | Vd | 10 | 10 | index_align | Rm
0xF980020F VST3{<c>}{<q>}.<size> <list>, [<Rn>] T32 111110011 | D | 0 | 0 | Rn | Vd | 00 | 10 | index_align | 1111
0xF980020D VST3{<c>}{<q>}.<size> <list>, [<Rn>]! T32 111110011 | D | 0 | 0 | Rn | Vd | 00 | 10 | index_align | 1101
0xF9800200 VST3{<c>}{<q>}.<size> <list>, [<Rn>], <Rm> T32 111110011 | D | 0 | 0 | Rn | Vd | 00 | 10 | index_align | Rm
0xF980060F VST3{<c>}{<q>}.<size> <list>, [<Rn>] T32 111110011 | D | 0 | 0 | Rn | Vd | 01 | 10 | index_align | 1111
0xF980060D VST3{<c>}{<q>}.<size> <list>, [<Rn>]! T32 111110011 | D | 0 | 0 | Rn | Vd | 01 | 10 | index_align | 1101

Description

Store single 3-element structure from one lane of three registers stores one 3-element structure to memory from corresponding elements of three registers. For details of the addressing mode, see Advanced SIMD addressing mode. Depending on settings in the CPACR, NSACR, and HCPTR registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be undefined, or trapped to Hyp mode. For more information, see Enabling Advanced SIMD and floating-point support.

Operation

if ConditionPassed() then
    EncodingSpecificOperations();  CheckAdvSIMDEnabled();
    address = R[n];
    MemU[address,         ebytes] = Elem[D[d], index,8*ebytes];
    MemU[address+ebytes,  ebytes] = Elem[D[d2],index,8*ebytes];
    MemU[address+2*ebytes,ebytes] = Elem[D[d3],index,8*ebytes];
    if wback then
        if register_index then
            R[n] = R[n] + R[m];
        else
            R[n] = R[n] + 3*ebytes;