frintz
Floating-Point Round to Integral (Zero)
FRINTZ <Hd|Sd|Dd>, <Hn|Sn|Dn>
Rounds float to integral value towards zero (Truncate).
Details
Rounds the floating-point value in the source register to the nearest integer towards zero (truncation), and writes the result to the destination register. The instruction does not set any condition flags (N, Z, C, V remain unaffected). Execution is AArch64-only and may generate floating-point exceptions based on the source operand and enabled exception controls.
Pseudocode Operation
Vd ← RoundTowardsZero(Vn)Example
FRINTZ Dd, Dn
Encoding
Binary Layout
0
0
0
11110
00
1001
011
10000
Rn
Rd
Operands
-
Vd
Destination SIMD/FP vector register -
Vn
First source SIMD/FP vector register
Reference (Arm A64 ISA)
Instruction Forms
| Encoding | Instruction | ISA | Bit pattern | ||
|---|---|---|---|---|---|
| 0x6503A000 | FRINTZ <Zd>.<T>, <Pg>/M, <Zn>.<T> | A64 | 01100101 | size | 000 | 01 | 1 | 101 | Pg | Zn | Zd | ||
| 0x0EF99800 | FRINTZ <Vd>.<T>, <Vn>.<T> | A64 | 0 | Q | 0 | 01110 | 1 | 1111001100 | 1 | 10 | Rn | Rd | ||
| 0x0EA19800 | FRINTZ <Vd>.<T>, <Vn>.<T> | A64 | 0 | Q | 0 | 01110 | 1 | sz | 100001100 | 1 | 10 | Rn | Rd | ||
| 0x1EE5C000 | FRINTZ <Hd>, <Hn> | A64 | 0 | 0 | 0 | 11110 | 11 | 1001 | 011 | 10000 | Rn | Rd | ||
| 0x1E25C000 | FRINTZ <Sd>, <Sn> | A64 | 0 | 0 | 0 | 11110 | 00 | 1001 | 011 | 10000 | Rn | Rd | ||
| 0x1E65C000 | FRINTZ <Dd>, <Dn> | A64 | 0 | 0 | 0 | 11110 | 01 | 1001 | 011 | 10000 | Rn | Rd |
Description
Floating-point Round to Integral, toward Zero (scalar). This instruction rounds a floating-point value in the SIMD&FP source register to an integral floating-point value of the same size using the Round towards Zero rounding mode, and writes the result to the SIMD&FP destination register.
A zero input gives a zero result with the same sign, an infinite input gives an infinite result with the same sign, and a NaN is propagated as for normal arithmetic.
A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.
Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Operation
CheckFPEnabled64(); boolean merge = IsMerging(FPCR); bits(128) result = if merge then V[d, 128] else Zeros(128); bits(esize) operand = V[n, esize]; Elem[result, 0, esize] = FPRoundInt(operand, FPCR, rounding, FALSE); V[d, 128] = result;