scvtf

Signed Integer Convert to Floating-Point

SCVTF <Hd|Sd|Dd>, <Wn|Xn> {, #<fbits>}

Converts signed integer (GPR) to floating-point.

Pseudocode Operation

int_val ← SignExtend(Rn)
if fbits != 0 then
  fp_val ← ConvertToFP(int_val / 2^fbits)
else
  fp_val ← ConvertToFP(int_val)
Vd ← fp_val

Example

SCVTF Dd, Wn

Encoding

Binary Layout

0

31

0

30

0

29

11110

28:24

00

23:22

1

21

00

20:19

010

18:16

000000

15:10

Rn

9:5

Rd

4:0

 

Format FP Conversion

Opcode 0x1E220000

Extension Floating Point

Operands

• Hd|Sd|Dd
  Destination SIMD&FP register (half, single or double-precision)
• Wn|Xn
  First source general-purpose register (32-bit/64-bit)

Related

Other forms of scvtf

• scvtf SVE Signed Integer Convert to Floating-Point
• scvtf Signed Integer Convert to Floating-point

More in Floating Point

Reference

View in Arm A64 ISA Reference ↗ Arm A64 ISA

Instruction Forms

Encoding	Instruction		ISA		Bit pattern
0x5F00E400	SCVTF <V><d>, <V><n>, #<fbits>		A64		01 | 0 | 111110 | immh | immb | 11100 | 1 | Rn | Rd
0x0F00E400	SCVTF <Vd>.<T>, <Vn>.<T>, #<fbits>		A64		0 | Q | 0 | 011110 | immh | immb | 11100 | 1 | Rn | Rd
0x5E79D800	SCVTF <Hd>, <Hn>		A64		01 | 0 | 11110 | 0 | 111100 | 11101 | 10 | Rn | Rd
0x5E21D800	SCVTF <V><d>, <V><n>		A64		01 | 0 | 111100 | sz | 10000 | 11101 | 10 | Rn | Rd
0x0E79D800	SCVTF <Vd>.<T>, <Vn>.<T>		A64		0 | Q | 0 | 01110 | 0 | 111100 | 11101 | 10 | Rn | Rd
0x0E21D800	SCVTF <Vd>.<T>, <Vn>.<T>		A64		0 | Q | 0 | 011100 | sz | 10000 | 11101 | 10 | Rn | Rd
0x1EC20000	SCVTF <Hd>, <Wn>, #<fbits>		A64		0 | 0 | 0 | 11110 | 11 | 0 | 00 | 010 | scale | Rn | Rd
0x9EC20000	SCVTF <Hd>, <Xn>, #<fbits>		A64		1 | 0 | 0 | 11110 | 11 | 0 | 00 | 010 | scale | Rn | Rd
0x1E020000	SCVTF <Sd>, <Wn>, #<fbits>		A64		0 | 0 | 0 | 11110 | 00 | 0 | 00 | 010 | scale | Rn | Rd
0x9E020000	SCVTF <Sd>, <Xn>, #<fbits>		A64		1 | 0 | 0 | 11110 | 00 | 0 | 00 | 010 | scale | Rn | Rd
0x1E420000	SCVTF <Dd>, <Wn>, #<fbits>		A64		0 | 0 | 0 | 11110 | 01 | 0 | 00 | 010 | scale | Rn | Rd
0x9E420000	SCVTF <Dd>, <Xn>, #<fbits>		A64		1 | 0 | 0 | 11110 | 01 | 0 | 00 | 010 | scale | Rn | Rd
0x1EE20000	SCVTF <Hd>, <Wn>		A64		0 | 0 | 0 | 11110 | 11 | 1 | 00 | 010 | 000000 | Rn | Rd
0x1E220000	SCVTF <Sd>, <Wn>		A64		0 | 0 | 0 | 11110 | 00 | 1 | 00 | 010 | 000000 | Rn | Rd

Description

Signed integer Convert to Floating-point (scalar). This instruction converts the signed integer value in the general-purpose source register to a floating-point value using the rounding mode that is specified by the FPCR, and writes the result to the SIMD&FP destination register. A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps. Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

Operation

CheckFPEnabled64();

constant boolean merge = IsMerging(FPCR);
constant integer fltsize = if merge then 128 else decode_fltsize;
bits(fltsize) fltval;
bits(intsize) intval;

intval = X[n, intsize];
fltval = if merge then V[d, fltsize] else Zeros(fltsize);
Elem[fltval, 0, decode_fltsize] = FixedToFP(intval, 0, FALSE, FPCR, rounding, decode_fltsize);
V[d, fltsize] = fltval;