svc

Supervisor Call (A32)

SVC<c> #<imm>

System call (formerly SWI).

Details

Generates a supervisor call exception, transferring control to the exception handler in supervisor mode. The 24-bit immediate is passed to the exception handler as optional information but does not affect the processor state directly. The instruction saves the return address in LR and updates the PC to the vector address. Condition flags are not modified by the exception itself.

Pseudocode Operation

saved_lr ← PC + 4
PC ← SupervisorCallVector
LR_svc ← saved_lr
CPSR.M ← 0b10011  // Supervisor mode

Example

SVC #16

Encoding

Binary Layout

cond

1111

imm24

Format System

Opcode 0x0F000000

Extension A32 (System)

Operands

imm
ID

Reference (Arm AArch32 ISA)

Instruction Forms

Encoding	Instruction		ISA		Bit pattern
0x0F000000	SVC{<c>}{<q>} {#}<imm>		A32		cond \| 1111 \| imm24
0xDF00	SVC{<c>}{<q>} {#}<imm>		T32		1101111 \| 1 \| imm8

Description

Supervisor Call causes a Supervisor Call exception. For more information, see Supervisor Call (SVC) exception. Software can use this instruction as a call to an operating system to provide a service. In the following cases, the Supervisor Call exception generated by the SVC instruction is taken to Hyp mode: In these cases, the HSR, Hyp Syndrome Register identifies that the exception entry was caused by a Supervisor Call exception, EC value 0x11, see Use of the HSR. The immediate field in the HSR:

Operation

if ConditionPassed() then
    EncodingSpecificOperations();
    AArch32.CheckForSVCTrap(imm32<15:0>);
    AArch32.CallSupervisor(imm32<15:0>);