vldm

Vector Load Multiple (VFP)

VLDM<c><mode> <Rn>{!}, <list>

Loads multiple VFP registers from memory.

Details

Vector Load Multiple loads multiple consecutive double-precision or single-precision floating-point registers from memory using the address in a general-purpose base register. The base register can be optionally auto-incremented by the total bytes loaded. Condition flags (N, Z, C, V) are unaffected unless an exception occurs.

Pseudocode Operation

address ← Rn; for i = 0 to (list_count - 1) do; Driestlist[i] ← [address]; address ← address + (register_size / 8); end; if !(!) then Rn ← address;

Example

VLDMia r1!, {r0-r3

Encoding

Binary Layout
cond
110
0
1
D
W
1
Rn
Vd
10
10
imm8
 
Format VFP Load Multiple
Opcode 0x0C900A00
Extension VFP (Float)

Operands

  • Rn
    First source / base general-purpose register
  • list
    Registers

Reference (Arm AArch32 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0x0C900B00 VLDM{<c>}{<q>}{.<size>} <Rn>{!}, <dreglist> A32 cond | 110 | 0 | 1 | D | W | 1 | Rn | Vd | 10 | 11 | imm8<7:1> | 0
0x0C900A00 VLDM{<c>}{<q>}{.<size>} <Rn>{!}, <sreglist> A32 cond | 110 | 0 | 1 | D | W | 1 | Rn | Vd | 10 | 10 | imm8
0xEC900B00 VLDM{<c>}{<q>}{.<size>} <Rn>{!}, <dreglist> T32 1110110 | 0 | 1 | D | W | 1 | Rn | Vd | 10 | 11 | imm8<7:1> | 0
0xEC900A00 VLDM{<c>}{<q>}{.<size>} <Rn>{!}, <sreglist> T32 1110110 | 0 | 1 | D | W | 1 | Rn | Vd | 10 | 10 | imm8

Description

Load Multiple SIMD&FP registers loads multiple registers from consecutive locations in the Advanced SIMD and floating-point register file using an address from a general-purpose register. Depending on settings in the CPACR, NSACR, and HCPTR registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be undefined, or trapped to Hyp mode. For more information, see Enabling Advanced SIMD and floating-point support.

Operation

if ConditionPassed() then
    EncodingSpecificOperations();
    CheckVFPEnabled(TRUE);
    address = if add then R[n] else R[n]-imm32;

    for r = 0 to regs-1
        if single_regs then
            S[d+r] = MemA[address,4];
            address = address+4;
        else
            word1 = MemA[address,4];
            word2 = MemA[address+4,4];
            address = address+8;

            // Combine the word-aligned words in the correct order for current endianness.
            D[d+r] = if BigEndian(AccessType_ASIMD) then word1:word2 else word2:word1;

    if wback then R[n] = if add then R[n]+imm32 else R[n]-imm32;