vpop

Vector Pop (VFP)

VPOP <list>

Pops VFP registers from the stack (Alias for VLDMIA SP!).

Details

Pops VFP floating-point registers from the stack by loading them from memory at the address in SP, then post-incrementing SP. This is an alias for VLDMIA SP! (VFP Load Multiple with post-index). The condition flags (N, Z, C, V) are unaffected by this instruction. Execution is restricted to A32 and T32 instruction sets with VFP extension enabled.

Pseudocode Operation

address ← SP; for each register in list (in ascending order): register ← [address]; address ← address + 4 or 8 (depending on register width); SP ← address;

Example

VPOP {r0-r3

Encoding

Binary Layout
cond
110
0
1
D
1
1
1101
Vd
10
10
imm8
 
Format VFP Load Multiple
Opcode 0x0CBD0A00
Extension VFP (Float)

Operands

  • list
    Register List

Reference (Arm AArch32 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0x0CBD0B00 VPOP{<c>}{<q>}{.<size>} <dreglist> A32 cond | 110 | 0 | 1 | D | 1 | 1 | 1101 | Vd | 10 | 11 | imm8<7:1> | 0
0x0CBD0A00 VPOP{<c>}{<q>}{.<size>} <sreglist> A32 cond | 110 | 0 | 1 | D | 1 | 1 | 1101 | Vd | 10 | 10 | imm8
0xECBD0B00 VPOP{<c>}{<q>}{.<size>} <dreglist> T32 1110110 | 0 | 1 | D | 1 | 1 | 1101 | Vd | 10 | 11 | imm8<7:1> | 0
0xECBD0A00 VPOP{<c>}{<q>}{.<size>} <sreglist> T32 1110110 | 0 | 1 | D | 1 | 1 | 1101 | Vd | 10 | 10 | imm8

Description

Pop SIMD&FP registers from stack loads multiple consecutive Advanced SIMD and floating-point register file registers from the stack.