stp

Store Pair SIMD&FP Registers

STP <St1|Dt1|Qt1>, <St2|Dt2|Qt2>, [<Xn|SP>, #<imm>]

Stores two floating-point/SIMD registers.

Details

The Store Pair SIMD&FP Registers instruction stores two floating-point/SIMD registers.

Pseudocode Operation

Memory[address] ← Vt2

Example

STP Qt1, Qt2, [x1, #16]

Encoding

Binary Layout
00101101
00
0
imm7
Rt2
Rn
Rt1
 
Format Load/Store Pair
Opcode 0x2D000000
Extension Floating Point

Operands

  • Vt1
    First transfer SIMD/FP register (load/store)
  • Vt2
    Second transfer SIMD/FP register (load/store)
  • Xn
    First source / base 64-bit integer register
  • imm
    Signed immediate value