stp

Store Pair SIMD&FP Registers

STP <St1|Dt1|Qt1>, <St2|Dt2|Qt2>, [<Xn|SP>, #<imm>]

Stores two floating-point/SIMD registers.

Details

Stores two consecutive floating-point or SIMD vector registers to memory at an address calculated from a base register and a scaled signed immediate offset. The two values are stored atomically as a pair, and no condition flags are affected. Execution is AArch64-only; the immediate is scaled by the operand size (4 bytes for 32-bit, 8 bytes for 64-bit, 16 bytes for 128-bit).

Pseudocode Operation

address ← (Xn | SP) + (imm7 << scale); [address] ← Vt1; [address + operand_size] ← Vt2

Example

STP Qt1, Qt2, [x1, #16]

Encoding

Binary Layout
00
101
1
010
0
imm7
Rt2
Rn
Rt
 
Format Load/Store Pair
Opcode 0x2D000000
Extension Floating Point

Operands

  • Vt1
    First transfer SIMD/FP register (load/store)
  • Vt2
    Second transfer SIMD/FP register (load/store)
  • Xn
    First source / base 64-bit integer register
  • imm
    Signed immediate value

Reference (Arm A64 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0x2C800000 STP <St1>, <St2>, [<Xn|SP>], #<imm> A64 00 | 101 | 1 | 001 | 0 | imm7 | Rt2 | Rn | Rt
0x6C800000 STP <Dt1>, <Dt2>, [<Xn|SP>], #<imm> A64 01 | 101 | 1 | 001 | 0 | imm7 | Rt2 | Rn | Rt
0xAC800000 STP <Qt1>, <Qt2>, [<Xn|SP>], #<imm> A64 10 | 101 | 1 | 001 | 0 | imm7 | Rt2 | Rn | Rt
0x2D800000 STP <St1>, <St2>, [<Xn|SP>, #<imm>]! A64 00 | 101 | 1 | 011 | 0 | imm7 | Rt2 | Rn | Rt
0x6D800000 STP <Dt1>, <Dt2>, [<Xn|SP>, #<imm>]! A64 01 | 101 | 1 | 011 | 0 | imm7 | Rt2 | Rn | Rt
0xAD800000 STP <Qt1>, <Qt2>, [<Xn|SP>, #<imm>]! A64 10 | 101 | 1 | 011 | 0 | imm7 | Rt2 | Rn | Rt
0x2D000000 STP <St1>, <St2>, [<Xn|SP>{, #<imm>}] A64 00 | 101 | 1 | 010 | 0 | imm7 | Rt2 | Rn | Rt
0x6D000000 STP <Dt1>, <Dt2>, [<Xn|SP>{, #<imm>}] A64 01 | 101 | 1 | 010 | 0 | imm7 | Rt2 | Rn | Rt
0xAD000000 STP <Qt1>, <Qt2>, [<Xn|SP>{, #<imm>}] A64 10 | 101 | 1 | 010 | 0 | imm7 | Rt2 | Rn | Rt
0x28800000 STP <Wt1>, <Wt2>, [<Xn|SP>], #<imm> A64 00 | 101 | 0 | 001 | 0 | imm7 | Rt2 | Rn | Rt
0xA8800000 STP <Xt1>, <Xt2>, [<Xn|SP>], #<imm> A64 10 | 101 | 0 | 001 | 0 | imm7 | Rt2 | Rn | Rt
0x29800000 STP <Wt1>, <Wt2>, [<Xn|SP>, #<imm>]! A64 00 | 101 | 0 | 011 | 0 | imm7 | Rt2 | Rn | Rt
0xA9800000 STP <Xt1>, <Xt2>, [<Xn|SP>, #<imm>]! A64 10 | 101 | 0 | 011 | 0 | imm7 | Rt2 | Rn | Rt
0x29000000 STP <Wt1>, <Wt2>, [<Xn|SP>{, #<imm>}] A64 00 | 101 | 0 | 010 | 0 | imm7 | Rt2 | Rn | Rt

Description

Store Pair of SIMD&FP registers. This instruction stores a pair of SIMD&FP registers to memory. The address used for the store is calculated from a base register value and an immediate offset. Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

Operation

CheckFPEnabled64();
bits(64) address;
bits(64) address2;
bits(datasize) data1;
bits(datasize) data2;
constant integer dbytes = datasize DIV 8;

AccessDescriptor accdesc = CreateAccDescASIMD(MemOp_STORE, FALSE, tagchecked);

if n == 31 then
    CheckSPAlignment();
    address = SP[];
else
    address = X[n, 64];

if !postindex then
    address = GenerateAddress(address, offset, accdesc);

data1 = V[t, datasize];
data2 = V[t2, datasize];
address2 = GenerateAddress(address, dbytes, accdesc);
Mem[address, dbytes, accdesc] = data1;
Mem[address2, dbytes, accdesc] = data2;

if wback then
    if postindex then
        address = GenerateAddress(address, offset, accdesc);
    if n == 31 then
        SP[] = address;
    else
        X[n, 64] = address;