umax

Vector Unsigned Maximum

UMAX <Vd>.<T>, <Vn>.<T>, <Vm>.<T>

Returns larger unsigned integer per element.

Pseudocode Operation

for i = 0 to elements_in_vector(Q, size) - 1 do
  Vd[i] ← max_unsigned(Vn[i], Vm[i])
end for

Example

UMAX v0.4s.T, v1.4s.T, v2.4s.T

Encoding

Binary Layout

0

31

Q

30

1

29

01110

28:24

size

23:22

1

21

Rm

20:16

0110

15:12

0

11

1

10

Rn

9:5

Rd

4:0

 

Format SIMD Three Register

Opcode 0x2E206400

Extension NEON (SIMD)

Operands

• Vd
  Destination SIMD/FP vector register
• Vn
  First source SIMD/FP vector register
• Vm
  Second source SIMD/FP vector register

Related

Other forms of umax

• umax SVE Unsigned Maximum

More in NEON (SIMD)

Reference

View in Arm A64 ISA Reference ↗ Arm A64 ISA

Instruction Forms

Encoding	Instruction		ISA		Bit pattern
0x2E206400	UMAX <Vd>.<T>, <Vn>.<T>, <Vm>.<T>		A64		0 | Q | 1 | 01110 | size | 1 | Rm | 0110 | 0 | 1 | Rn | Rd
0x11C40000	UMAX <Wd>, <Wn>, #<uimm>		A64		0 | 0 | 0 | 1000111 | 0001 | imm8 | Rn | Rd
0x91C40000	UMAX <Xd>, <Xn>, #<uimm>		A64		1 | 0 | 0 | 1000111 | 0001 | imm8 | Rn | Rd
0xC120A001	UMAX { <Zdn1>.<T>-<Zdn2>.<T> }, { <Zdn1>.<T>-<Zdn2>.<T> }, <Zm>.<T>		A64		11000001 | size | 10 | Zm | 101000 | 0000 | 0 | Zdn | 1
0xC120A801	UMAX { <Zdn1>.<T>-<Zdn4>.<T> }, { <Zdn1>.<T>-<Zdn4>.<T> }, <Zm>.<T>		A64		11000001 | size | 10 | Zm | 101010 | 0000 | 0 | Zdn | 0 | 1
0xC120B001	UMAX { <Zdn1>.<T>-<Zdn2>.<T> }, { <Zdn1>.<T>-<Zdn2>.<T> }, { <Zm1>.<T>-<Zm2>.<T> }		A64		11000001 | size | 1 | Zm | 0101100 | 000 | 0 | 0 | Zdn | 1
0xC120B801	UMAX { <Zdn1>.<T>-<Zdn4>.<T> }, { <Zdn1>.<T>-<Zdn4>.<T> }, { <Zm1>.<T>-<Zm4>.<T> }		A64		11000001 | size | 1 | Zm | 00101110 | 000 | 0 | 0 | Zdn | 0 | 1
0x1AC06400	UMAX <Wd>, <Wn>, <Wm>		A64		0 | 0 | 0 | 11010110 | Rm | 011001 | Rn | Rd
0x9AC06400	UMAX <Xd>, <Xn>, <Xm>		A64		1 | 0 | 0 | 11010110 | Rm | 011001 | Rn | Rd
0x04090000	UMAX <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>		A64		00000100 | size | 001 | 0 | 0 | 1 | 000 | Pg | Zm | Zdn
0x2529C000	UMAX <Zdn>.<T>, <Zdn>.<T>, #<imm>		A64		00100101 | size | 101 | 00 | 1 | 11 | 0 | imm8 | Zdn

Description

Unsigned Maximum (vector). This instruction compares corresponding elements in the vectors in the two source SIMD&FP registers, places the larger of each pair of unsigned integer values into a vector, and writes the vector to the destination SIMD&FP register. Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = V[n, datasize];
bits(datasize) operand2 = V[m, datasize];
bits(datasize) result;
integer element1;
integer element2;
integer maxmin;

for e = 0 to elements-1
    element1 = Int(Elem[operand1, e, esize], unsigned);
    element2 = Int(Elem[operand2, e, esize], unsigned);
    maxmin = if minimum then Min(element1, element2) else Max(element1, element2);
    Elem[result, e, esize] = maxmin<esize-1:0>;

V[d, datasize] = result;