vaddl

Vector Add Long

VADDL<c>.<dt> <Qd>, <Dn>, <Dm>

Adds N-bit elements, producing 2N-bit results.

Details

Adds corresponding N-bit elements from two 64-bit NEON registers and produces 2N-bit results stored in a 128-bit register. This instruction performs widening addition, doubling the element width and producing twice as many result bits. No flags are affected.

Pseudocode Operation

for i = 0 to pairs-1
  Qd[i] ← Dn[i] + Dm[i]

Example

VADDL.dt q0, d1, d2

Encoding

Binary Layout
1111001
U
1
D
size
Vn
Vd
000
0
N
0
M
0
Vm
 
Format NEON 3-Reg
Opcode 0xF2800000
Extension NEON (SIMD)

Operands

  • Qd
    Dest Wide
  • Dn
    First source 64-bit SIMD/FP register
  • Dm
    Second source 64-bit SIMD/FP register

Reference (Arm AArch32 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0xF2800000 VADDL{<c>}{<q>}.<dt> <Qd>, <Dn>, <Dm> A32 1111001 | U | 1 | D | size | Vn | Vd | 000 | 0 | N | 0 | M | 0 | Vm
0xEF800000 VADDL{<c>}{<q>}.<dt> <Qd>, <Dn>, <Dm> T32 111 | U | 11111 | D | size | Vn | Vd | 000 | 0 | N | 0 | M | 0 | Vm

Description

Vector Add Long adds corresponding elements in two doubleword vectors, and places the results in a quadword vector. Before adding, it sign-extends or zero-extends the elements of both operands. Depending on settings in the CPACR, NSACR, and HCPTR registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be undefined, or trapped to Hyp mode. For more information see Enabling Advanced SIMD and floating-point support.

Operation

if ConditionPassed() then
    EncodingSpecificOperations();  CheckAdvSIMDEnabled();
    for e = 0 to elements-1
        integer op1;
        if is_vaddw then
            op1 = Int(Elem[Qin[n>>1],e,2*esize], unsigned);
        else
            op1 = Int(Elem[Din[n],e,esize], unsigned);
        result = op1 + Int(Elem[Din[m],e,esize],unsigned);
        Elem[Q[d>>1],e,2*esize] = result<2*esize-1:0>;