bfmmla

BFloat16 Matrix Multiply-Accumulate (NEON)

BFMMLA <Vd>.<T>, <Vn>.<T>, <Vm>.<T>

Performs 2x2 matrix multiplication on BFloat16 tiles (NEON).

Pseudocode Operation

for i = 0 to 1 do
  for j = 0 to 1 do
    sum ← Vd[i*2+j]
    for k = 0 to 1 do
      sum ← sum + (BF16_to_F32(Vn[i*2+k]) × BF16_to_F32(Vm[k*2+j]))
    end for
    Vd[i*2+j] ← sum
  end for
end for

Example

BFMMLA v0.4s.T, v1.4s.T, v2.4s.T

Encoding

Binary Layout

0

31

1

30

1

29

01110

28:24

01

23:22

0

21

Rm

20:16

1

15

1101

14:11

1

10

Rn

9:5

Rd

4:0

 

Format NEON 3-Reg

Opcode 0x6E40EC00

Extension FEAT_BF16 (AI)

Operands

• Vd
  Destination SIMD/FP vector register
• Vn
  First source SIMD/FP vector register
• Vm
  Second source SIMD/FP vector register

Related

More in FEAT_BF16 (AI)

Reference

View in Arm A64 ISA Reference ↗ Arm A64 ISA

Instruction Forms

Encoding	Instruction		ISA		Bit pattern
0x6E40EC00	BFMMLA <Vd>.4S, <Vn>.8H, <Vm>.8H		A64		0 | 1 | 1 | 01110 | 01 | 0 | Rm | 1 | 1101 | 1 | Rn | Rd
0x6460E400	BFMMLA <Zda>.S, <Zn>.H, <Zm>.H		A64		01100100 | 0 | 1 | 1 | Zm | 111001 | Zn | Zda

Description

BFloat16 floating-point matrix multiply-accumulate into 2x2 matrix. If FEAT_EBF16 is not implemented or FPCR.EBF is 0, this instruction: If FEAT_EBF16 is implemented and FPCR.EBF is 1, then this instruction: Irrespective of FEAT_EBF16 and FPCR.EBF, this instruction: ID_AA64ISAR1_EL1.BF16 indicates whether this instruction is supported.

Operation

CheckFPAdvSIMDEnabled64();
bits(128) op1 = V[n, 128];
bits(128) op2 = V[m, 128];
bits(128) acc = V[d, 128];

V[d, 128] = BFMatMulAdd(acc, op1, op2, FPCR);