adds

Add and Set Flags (Extended Register 64-bit)

ADDS <Xd>, <Xn|SP>, <R><m> {, <extend> {#<amount>}}

Adds and updates flags (Extended Register 64-bit).

Details

Add with extended register operand and set condition flags. Adds the sign-extended or zero-extended value of Rm to Xn, stores the result in Xd, and updates the N, Z, C, and V flags based on the result. AArch64-only instruction executing at any privilege level.

Pseudocode Operation

result ← Xn + ExtendValue(Rm, extend, amount)
Xd ← result
N ← result[63]
Z ← (result == 0)
C ← CarryOut(Xn, ExtendValue(Rm, extend, amount))
V ← OverflowFrom(Xn, ExtendValue(Rm, extend, amount))

Example

ADDS x0, x1, Rm

Encoding

Binary Layout
1
0
1
01011
00
1
Rm
option
imm3
Rn
Rd
 
Format Data Processing (Register)
Opcode 0xAB200000
Extension Base

Operands

  • Xd
    Destination 64-bit integer register
  • Xn
    First source / base 64-bit integer register
  • Rm
    Second source / offset general-purpose register

Reference (Arm A64 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0x2B200000 ADDS <Wd>, <Wn|WSP>, <Wm>{, <extend> {#<amount>}} A64 0 | 0 | 1 | 01011 | 00 | 1 | Rm | option | imm3 | Rn | Rd
0xAB200000 ADDS <Xd>, <Xn|SP>, <R><m>{, <extend> {#<amount>}} A64 1 | 0 | 1 | 01011 | 00 | 1 | Rm | option | imm3 | Rn | Rd
0x31000000 ADDS <Wd>, <Wn|WSP>, #<imm>{, <shift>} A64 0 | 0 | 1 | 100010 | sh | imm12 | Rn | Rd
0xB1000000 ADDS <Xd>, <Xn|SP>, #<imm>{, <shift>} A64 1 | 0 | 1 | 100010 | sh | imm12 | Rn | Rd
0x2B000000 ADDS <Wd>, <Wn>, <Wm>{, <shift> #<amount>} A64 0 | 0 | 1 | 01011 | shift | 0 | Rm | imm6 | Rn | Rd
0xAB000000 ADDS <Xd>, <Xn>, <Xm>{, <shift> #<amount>} A64 1 | 0 | 1 | 01011 | shift | 0 | Rm | imm6 | Rn | Rd

Description

Add (extended register), setting flags, adds a register value and a sign or zero-extended register value, followed by an optional left shift amount, and writes the result to the destination register. The argument that is extended from the <Rm> register can be a byte, halfword, word, or doubleword. It updates the condition flags based on the result.

Operation

bits(datasize) result;
bits(datasize) operand1 = if n == 31 then SP[]<datasize-1:0> else X[n, datasize];
bits(datasize) operand2 = ExtendReg(m, extend_type, shift, datasize);
bits(4) nzcv;


(result, nzcv) = AddWithCarry(operand1, operand2, '0');

PSTATE.<N,Z,C,V> = nzcv;

X[d, datasize] = result;