swp

Swap (A32)

SWP<c> <Rt>, <Rt2>, [<Rn>]

Atomic swap word (Legacy).

Details

Atomically loads a word from memory at [Rn], writes Rt2 to that address, and stores the loaded value in Rt. This is a legacy ARMv5 and earlier instruction; ARMv6 and later code should use LDREX/STREX or LDAEX/STLEX for synchronization. No condition flags are affected. Memory ordering is not guaranteed; for ordered access use SWP with appropriate memory barriers.

Pseudocode Operation

temp ← [Rn]
[Rn] ← Rt2
Rt ← temp

Example

SWP r3, r4, [r1]

Encoding

Binary Layout
10
111
0
00
0
0
1
Rs
1
000
00
Rn
Rt
 
Format Load/Store
Opcode 0xB8208000
Extension A32 (Atomic)

Operands

  • Rt
    Transfer general-purpose register (load/store)
  • Rt2
    Second transfer register (load/store pair)
  • Rn
    Addr

Reference (Arm A64 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0xB8208000 SWP <Ws>, <Wt>, [<Xn|SP>] A64 10 | 111 | 0 | 00 | 0 | 0 | 1 | Rs | 1 | 000 | 00 | Rn | Rt
0xF8208000 SWP <Xs>, <Xt>, [<Xn|SP>] A64 11 | 111 | 0 | 00 | 0 | 0 | 1 | Rs | 1 | 000 | 00 | Rn | Rt

Description

Swap word or doubleword in memory atomically loads a 32-bit word or 64-bit doubleword from a memory location, and stores the value held in a register back to the same memory location. The value initially loaded from memory is returned in the destination register. For more information about memory ordering semantics, see Load-Acquire, Store-Release. For information about memory accesses, see Load/Store addressing modes.

Operation

bits(64) address;
bits(datasize) data;
bits(datasize) store_value;
AccessDescriptor accdesc = CreateAccDescAtomicOp(MemAtomicOp_SWP, acquire, release, tagchecked);

if n == 31 then
    CheckSPAlignment();
    address = SP[];
else
    address = X[n, 64];

store_value = X[s, datasize];

bits(datasize) comparevalue = bits(datasize) UNKNOWN;    // Irrelevant when not executing CAS
data = MemAtomic(address, comparevalue, store_value, accdesc);

X[t, regsize] = ZeroExtend(data, regsize);