bic

Bitwise Bit Clear (Shifted Register)

BIC <Wd>, <Wn>, <Wm> {, <shift> #<amount>}

ANDs register with NOT of shifted register (AND NOT).

Pseudocode Operation

operand2 ← DecodeShift(Wm, shift, amount)
Wd ← Wn AND NOT operand2
if Wd[31] == 1 then N ← 1 else N ← 0
if Wd == 0 then Z ← 1 else Z ← 0

Example

BIC w0, w1, w2

Encoding

Binary Layout

0

31

00

30:29

01010

28:24

shift

23:22

1

21

Rm

20:16

imm6

15:10

Rn

9:5

Rd

4:0

 

Format Logical (Register)

Opcode 0x0A200000

Extension Base

Operands

• Wd
  Destination 32-bit integer register
• Wn
  First source / base 32-bit integer register
• Wm
  Second source / offset 32-bit integer register

Related

Other forms of bic

• bic Bitwise Bit Clear (Shifted Register 64-bit)
• bic Vector Bitwise Bit Clear
• bic SVE Bitwise Bit Clear (Predicated)
• bic Bit Clear (A32)

More in Base

Reference

View in Arm A64 ISA Reference ↗ Arm A64 ISA

Instruction Forms

Encoding	Instruction		ISA		Bit pattern
0x2F009400	BIC <Vd>.<T>, #<imm8>{, LSL #<amount>}		A64		0 | Q | 1 | 0111100000 | a | b | c | cmode | 0 | 1 | d | e | f | g | h | Rd
0x2F001400	BIC <Vd>.<T>, #<imm8>{, LSL #<amount>}		A64		0 | Q | 1 | 0111100000 | a | b | c | cmode | 0 | 1 | d | e | f | g | h | Rd
0x0E601C00	BIC <Vd>.<T>, <Vn>.<T>, <Vm>.<T>		A64		0 | Q | 0 | 01110 | 01 | 1 | Rm | 00011 | 1 | Rn | Rd
0x05800000	BIC <Zdn>.<T>, <Zdn>.<T>, #<const>		A64		00000101 | 1 | 0 | 0000 | imm13 | Zdn
0x0A200000	BIC <Wd>, <Wn>, <Wm>{, <shift> #<amount>}		A64		0 | 00 | 01010 | shift | 1 | Rm | imm6 | Rn | Rd
0x8A200000	BIC <Xd>, <Xn>, <Xm>{, <shift> #<amount>}		A64		1 | 00 | 01010 | shift | 1 | Rm | imm6 | Rn | Rd
0x25004010	BIC <Pd>.B, <Pg>/Z, <Pn>.B, <Pm>.B		A64		00100101 | 0 | 0 | 00 | Pm | 01 | Pg | 0 | Pn | 1 | Pd
0x041B0000	BIC <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>		A64		00000100 | size | 011 | 01 | 1 | 000 | Pg | Zm | Zdn
0x04E03000	BIC <Zd>.D, <Zn>.D, <Zm>.D		A64		00000100 | 1 | 1 | 1 | Zm | 001100 | Zn | Zd

Description

Bitwise Bit Clear (shifted register) performs a bitwise AND of a register value and the complement of an optionally-shifted register value, and writes the result to the destination register.

Operation

bits(datasize) operand1 = X[n, datasize];
bits(datasize) operand2 = ShiftReg(m, shift_type, shift_amount, datasize);
bits(datasize) result;

operand2 = NOT(operand2);

result = operand1 AND operand2;
X[d, datasize] = result;