saddw

Signed Add Wide

SADDW <Vd>.<Td>, <Vn>.<Td>, <Vm>.<Ts>

Adds a wide vector to the lower/upper half of a narrow vector.

Details

Adds each element of a narrow signed vector to the corresponding element of a wide signed vector (which is already the destination width), producing a result stored in the wide destination vector. Q=0 operates on lower half of Vm; Q=1 operates on upper half. No condition flags are affected; the instruction is AArch64 NEON-only with wrapping on overflow.

Pseudocode Operation

if Q == 0 then
  half ← "lower"
else
  half ← "upper"
for i = 0 to (length(Vd) / element_width(Td)) - 1 do
  Vn_element ← Vn[i]
  Vm_element ← extract_half(Vm[i], half)
  Vd[i] ← signed_add(Vn_element, Vm_element)
N ← unaffected; Z ← unaffected; C ← unaffected; V ← unaffected

Example

SADDW v0.4s.Td, v1.4s.Td, v2.4s.Ts

Encoding

Binary Layout
0
Q
0
01110
size
1
Rm
00
0
100
Rn
Rd
 
Format SIMD Three Register Diff
Opcode 0x0E201000
Extension NEON (SIMD)

Operands

  • Vd
    Destination SIMD/FP vector register
  • Vn
    Src Wide
  • Vm
    Src Narrow

Reference (Arm A64 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0x0E201000 SADDW{2} <Vd>.<Ta>, <Vn>.<Ta>, <Vm>.<Tb> A64 0 | Q | 0 | 01110 | size | 1 | Rm | 00 | 0 | 100 | Rn | Rd

Description

Signed Add Wide. This instruction adds vector elements of the first source SIMD&FP register to the corresponding vector elements in the lower or upper half of the second source SIMD&FP register, places the results in a vector, and writes the vector to the SIMD&FP destination register. The SADDW instruction extracts the second source vector from the lower half of the second source register. The SADDW2 instruction extracts the second source vector from the upper half of the second source register. Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

Operation

CheckFPAdvSIMDEnabled64();
bits(2*datasize) operand1 = V[n, 2*datasize];
bits(datasize) operand2 = Vpart[m, part, datasize];
bits(2*datasize) result;
integer element1;
integer element2;
integer sum;

for e = 0 to elements-1
    element1 = Int(Elem[operand1, e, 2*esize], unsigned);
    element2 = Int(Elem[operand2, e, esize], unsigned);
    if sub_op then
        sum = element1 - element2;
    else
        sum = element1 + element2;
    Elem[result, e, 2*esize] = sum<2*esize-1:0>;

V[d, 2*datasize] = result;