ic
Instruction Cache Operation
IC <op> {, <Xt>}
Performs instruction cache maintenance.
Details
Instruction Cache Operation performs maintenance on the instruction cache, including invalidation and synchronization of instruction streams. The operation type is specified by op, and Xt provides the target address (optional for some operations). No condition flags are affected. AArch64-only; may require EL1 or higher depending on the operation.
Pseudocode Operation
ICacheMaintenance(op, address ← Xt); // Operation type determined by op, affecting IC_IALLU, IC_IVAU, IC_IALLUISExample
IC op
Encoding
Binary Layout
1101010100
0
01
op1
0111
CRm
op2
Rt
Operands
-
op
Operation (IALLU, IVAU) -
Xt
Address (Optional)
Reference (Arm A64 ISA)
Instruction Forms
| Encoding | Instruction | ISA | Bit pattern | ||
|---|---|---|---|---|---|
| 0xD5087000 | IC <ic_op>{, <Xt>} | A64 | 1101010100 | 0 | 01 | op1 | 0111 | CRm | op2 | Rt |
Description
Instruction Cache operation. For more information, see op0==0b01, cache maintenance, TLB maintenance, and address translation instructions.